Searched refs:MDIO (Results 1 – 25 of 123) sorted by relevance
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| /Linux-v5.15/drivers/net/mdio/ |
| D | Kconfig | 3 # MDIO Layer Configuration
7 tristate "MDIO bus device drivers"
9 MDIO devices and driver infrastructure code.
27 FWNODE MDIO bus (Ethernet PHY) accessors
35 OpenFirmware MDIO bus (Ethernet PHY) accessors
42 ACPI MDIO bus (Ethernet PHY) accessors
50 tristate "Allwinner sun4i MDIO interface support"
53 This driver supports the MDIO interface found in the network
58 tristate "APM X-Gene SoC MDIO bus controller"
61 This module provides a driver for the MDIO busses found in the
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| /Linux-v5.15/Documentation/ABI/testing/ |
| D | sysfs-bus-mdio | 7 MDIO bus address statistics.
14 Total number of transfers for this MDIO bus.
21 Total number of transfer errors for this MDIO bus.
28 Total number of write transactions for this MDIO bus.
35 Total number of read transactions for this MDIO bus.
42 Total number of transfers for this MDIO bus address.
49 Total number of transfer errors for this MDIO bus address.
56 Total number of write transactions for this MDIO bus address.
63 Total number of read transactions for this MDIO bus address.
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| /Linux-v5.15/Documentation/firmware-guide/acpi/dsd/ |
| D | phy.rst | 4 MDIO bus and PHYs in ACPI
7 The PHYs on an MDIO bus [1] are probed and registered using
11 on the MDIO bus have to be referenced.
14 for connecting PHYs on the MDIO bus [3] to the MAC layer.
24 the PHY that is registered on an MDIO bus. This is mandatory for
25 network interfaces that have PHYs connected to MAC via MDIO bus.
27 During the MDIO bus driver initialization, PHYs on this bus are probed
28 using the _ADR object as shown below and are registered on the MDIO bus.
44 have to be retrieved from the MDIO bus. For this, the MAC driver needs
70 DSDT entry for MDIO node
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| /Linux-v5.15/Documentation/devicetree/bindings/net/ |
| D | marvell-orion-mdio.txt | 1 * Marvell MDIO Ethernet Controller interface
5 identical unit that provides an interface with the MDIO bus.
12 - reg: address and length of the MDIO registers. When an interrupt is
19 - clocks: phandle for up to four required clocks for the MDIO instance
21 The child nodes of the MDIO driver are the individual PHY devices
22 connected to this MDIO bus. They must have a "reg" property given the
23 PHY address on the MDIO bus.
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| D | cavium-mdio.txt | 1 * System Management Interface (SMI) / MDIO
11 - reg: The base address of the MDIO bus controller register bank.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
17 Typically an MDIO bus might have several children.
33 * System Management Interface (SMI) / MDIO Nexus
48 - ranges: As needed for mapping of the MDIO bus device registers.
50 - assigned-addresses: As needed for mapping of the MDIO bus device registers.
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| D | hisilicon-hns-mdio.txt | 1 Hisilicon MDIO bus controller
10 - reg: The base address of the MDIO bus controller register bank.
12 - #size-cells: Must be <0>. MDIO addresses have no size component.
14 Typically an MDIO bus might have several children.
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| D | mscc-miim.txt | 1 Microsemi MII Management Controller (MIIM) / MDIO
6 - reg: The base address of the MDIO bus controller register bank. Optionally, a
10 - #size-cells: Must be <0>. MDIO addresses have no size component.
13 Typically an MDIO bus might have several children.
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| D | brcm,mdio-mux-iproc.txt | 1 Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs.
3 This MDIO bus multiplexer defines buses that could be internal as well as
4 external to SoCs and could accept MDIO transaction compatible to C-22 or
6 properties as well to generate desired MDIO transaction on appropriate bus.
10 MDIO multiplexer node:
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| D | apm-xgene-mdio.txt | 1 APM X-Gene SoC MDIO node
3 MDIO node is defined to describe on-chip MDIO controller.
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| D | fsl-fman.txt | 10 - FMan MDIO Node
369 FMan MDIO Node
373 The MDIO is a bus to which the PHY devices are connected.
381 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
382 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
383 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
394 Definition: Specifies the external MDIO bus clock speed to
401 Usage: required for external MDIO
403 Definition: Event interrupt of external MDIO controller.
406 Usage: required for internal MDIO
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| D | mdio-mux-meson-g12a.txt | 1 Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.
3 This is a special case of a MDIO bus multiplexer. It allows to choose between
5 MDIO bus.
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| D | nixge.txt | 11 "ctrl": MDIO and PHY control and status region
19 - mdio subnode to indicate presence of MDIO controller
49 Examples (10G generic PHY, no MDIO):
65 Examples (1G generic fixed-link + MDIO):
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| D | fsl-enetc.txt | 14 1. The ENETC external port is connected to a MDIO configurable phy
16 1.1. Using the local ENETC Port MDIO interface
26 - phy-handle : Phandle to a PHY on the MDIO bus.
52 1.2. Using the central MDIO PCIe endpoint device
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| D | brcm,bcmgenet.txt | 28 when operating in a RGMII to RGMII type of connection, or when the MDIO bus is
38 MDIO bus node required properties:
45 - #address-cells: address cell for MDIO bus addressing, should be 1
46 - #size-cells: size of the cells for MDIO bus addressing, should be 0
100 External MDIO-connected Gigabit PHY/switch:
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| D | fsl-tsec-phy.txt | 1 * MDIO IO device
3 The MDIO is a bus to which the PHY devices are connected. For each
37 * TBI Internal MDIO bus
40 This PHY is accessed through the local MDIO bus. These buses are defined
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| /Linux-v5.15/arch/powerpc/boot/dts/ |
| D | kmeter1.dts | 148 0 1 3 0 2 0 /* MDIO */
174 0 1 3 0 2 0 /* MDIO */
200 0 1 3 0 2 0 /* MDIO */
220 0 1 3 0 2 0 /* MDIO */
238 0 1 3 0 2 0 /* MDIO */
256 0 1 3 0 2 0 /* MDIO */
274 0 1 3 0 2 0 /* MDIO */
314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
346 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
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| /Linux-v5.15/Documentation/devicetree/bindings/phy/ |
| D | brcm,mdio-mux-bus-pci.txt | 4 - reg: MDIO Bus number for the MDIO interface
10 - reg: MDIO Phy ID for the MDIO interface
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| /Linux-v5.15/Documentation/devicetree/bindings/net/dsa/ |
| D | realtek-smi.txt | 5 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
6 not use the MDIO protocol. This binding defines how to specify the
23 - mdio-gpios: GPIO line for the MDIO data line.
50 This defines the internal MDIO bus of the SMI device, mostly for the
58 See net/mdio.txt for additional MDIO bus properties.
67 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
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| D | marvell.txt | 10 Marvell Switches are MDIO devices. The following properties should be
17 which is at a different MDIO base address in different switch families.
44 - mdio : Container of PHY and devices on the switches MDIO
46 - mdio? : Container of PHYs and devices on the external MDIO
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| /Linux-v5.15/drivers/net/ethernet/freescale/ |
| D | Kconfig | 48 bool "FEC MPC52xx MDIO bus driver"
63 tristate "Freescale PQ MDIO"
66 This driver supports the MDIO bus used by the gianfar and UCC drivers.
69 tristate "Freescale XGMAC MDIO"
74 This driver supports the MDIO bus on the Fman 10G Ethernet MACs, and
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| /Linux-v5.15/drivers/net/dsa/xrs700x/ |
| D | Kconfig | 21 tristate "Arrow XRS7000X series switch in MDIO mode"
25 Enable MDIO support for Arrow SpeedChips XRS7003/7004 gigabit Ethernet
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| /Linux-v5.15/drivers/net/ethernet/freescale/fs_enet/ |
| D | Kconfig | 29 tristate "MDIO driver for FEC"
33 tristate "MDIO driver for FCC"
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| /Linux-v5.15/Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 17 - quad external Gigabit PHY w/ MDIO multiplexer
31 - ``SWITCH_MDIO``: external MDIO bus controller (there is another one in SWITCH_CORE,
66 MDIO indirect accesses
70 Broadcom switches connected to a SF2 require the use of the DSA slave MDIO bus
72 an external switch pseudo-PHY address will both be snooping for incoming MDIO
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| /Linux-v5.15/drivers/net/dsa/b53/ |
| D | Kconfig | 20 tristate "B53 MDIO connected switch driver"
23 Select to enable support for registering switches configured through MDIO.
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| /Linux-v5.15/arch/powerpc/platforms/pasemi/ |
| D | Kconfig | 45 tristate "MDIO support via GPIO"
48 Driver for MDIO via GPIO on PWRficient platforms
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