Searched refs:MCR_RTS (Results 1 – 9 of 9) sorted by relevance
66 #define MCR_RTS 0x02 macro308 priv->line_control |= MCR_RTS; in spcp8x5_set_termios()422 priv->line_control |= MCR_RTS; in spcp8x5_tiocmset()426 priv->line_control &= ~MCR_RTS; in spcp8x5_tiocmset()453 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in spcp8x5_tiocmget()
123 #define MCR_RTS 0x02 // Assert RTS macro
52 #define MCR_RTS 0x02 /* Assert RTS */ macro951 mos7840_port->shadowMCR &= ~MCR_RTS; in mos7840_throttle()981 mos7840_port->shadowMCR |= MCR_RTS; in mos7840_unthrottle()1004 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in mos7840_tiocmget()1027 mcr &= ~MCR_RTS; in mos7840_tiocmset()1034 mcr |= MCR_RTS; in mos7840_tiocmset()1286 mos7840_port->shadowMCR |= (MCR_DTR | MCR_RTS); in mos7840_change_port_settings()
1521 status = ti_do_config(port, UMPC_SET_CLR_RTS, mcr & MCR_RTS); in restore_mcr()1910 edge_port->shadow_mcr = MCR_RTS | MCR_DTR; in edge_open()2185 edge_port->shadow_mcr &= ~MCR_RTS; in stop_read()2203 edge_port->shadow_mcr |= MCR_RTS; in restart_read()2373 mcr |= MCR_RTS; in edge_tiocmset()2380 mcr &= ~MCR_RTS; in edge_tiocmset()2407 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ in edge_tiocmget()
1394 edge_port->shadowMCR &= ~MCR_RTS; in edge_throttle()1431 edge_port->shadowMCR |= MCR_RTS; in edge_unthrottle()1499 mcr |= MCR_RTS; in edge_tiocmset()1506 mcr &= ~MCR_RTS; in edge_tiocmset()1530 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ in edge_tiocmget()2466 edge_port->shadowMCR |= (MCR_DTR | MCR_RTS); in change_port_settings()
132 #define MCR_RTS 0x0200 /* Request to Send */ macro
123 #define MCR_RTS (1 << 1) /* Request to Send */ macro
73 #define MCR_RTS 0x02 macro
182 #define MCR_RTS 0x02 /* RTS output */ macro225 #define PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */305 outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase)); in fpga_reset()320 bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR; in fpga_write()
