1 /*
2 * Read/Write Loongson Extension Registers
3 */
4
5 #ifndef _LOONGSON_REGS_H_
6 #define _LOONGSON_REGS_H_
7
8 #include <linux/types.h>
9 #include <linux/bits.h>
10
11 #include <asm/mipsregs.h>
12 #include <asm/cpu.h>
13
cpu_has_cfg(void)14 static inline bool cpu_has_cfg(void)
15 {
16 return ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G);
17 }
18
read_cpucfg(u32 reg)19 static inline u32 read_cpucfg(u32 reg)
20 {
21 u32 __res;
22
23 __asm__ __volatile__(
24 "parse_r __res,%0\n\t"
25 "parse_r reg,%1\n\t"
26 ".insn \n\t"
27 ".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t"
28 :"=r"(__res)
29 :"r"(reg)
30 :
31 );
32 return __res;
33 }
34
35 /* Bit Domains for CFG registers */
36 #define LOONGSON_CFG0 0x0
37 #define LOONGSON_CFG0_PRID GENMASK(31, 0)
38
39 #define LOONGSON_CFG1 0x1
40 #define LOONGSON_CFG1_FP BIT(0)
41 #define LOONGSON_CFG1_FPREV GENMASK(3, 1)
42 #define LOONGSON_CFG1_MMI BIT(4)
43 #define LOONGSON_CFG1_MSA1 BIT(5)
44 #define LOONGSON_CFG1_MSA2 BIT(6)
45 #define LOONGSON_CFG1_CGP BIT(7)
46 #define LOONGSON_CFG1_WRP BIT(8)
47 #define LOONGSON_CFG1_LSX1 BIT(9)
48 #define LOONGSON_CFG1_LSX2 BIT(10)
49 #define LOONGSON_CFG1_LASX BIT(11)
50 #define LOONGSON_CFG1_R6FXP BIT(12)
51 #define LOONGSON_CFG1_R6CRCP BIT(13)
52 #define LOONGSON_CFG1_R6FPP BIT(14)
53 #define LOONGSON_CFG1_CNT64 BIT(15)
54 #define LOONGSON_CFG1_LSLDR0 BIT(16)
55 #define LOONGSON_CFG1_LSPREF BIT(17)
56 #define LOONGSON_CFG1_LSPREFX BIT(18)
57 #define LOONGSON_CFG1_LSSYNCI BIT(19)
58 #define LOONGSON_CFG1_LSUCA BIT(20)
59 #define LOONGSON_CFG1_LLSYNC BIT(21)
60 #define LOONGSON_CFG1_TGTSYNC BIT(22)
61 #define LOONGSON_CFG1_LLEXC BIT(23)
62 #define LOONGSON_CFG1_SCRAND BIT(24)
63 #define LOONGSON_CFG1_MUALP BIT(25)
64 #define LOONGSON_CFG1_KMUALEN BIT(26)
65 #define LOONGSON_CFG1_ITLBT BIT(27)
66 #define LOONGSON_CFG1_LSUPERF BIT(28)
67 #define LOONGSON_CFG1_SFBP BIT(29)
68 #define LOONGSON_CFG1_CDMAP BIT(30)
69
70 #define LOONGSON_CFG1_FPREV_OFFSET 1
71
72 #define LOONGSON_CFG2 0x2
73 #define LOONGSON_CFG2_LEXT1 BIT(0)
74 #define LOONGSON_CFG2_LEXT2 BIT(1)
75 #define LOONGSON_CFG2_LEXT3 BIT(2)
76 #define LOONGSON_CFG2_LSPW BIT(3)
77 #define LOONGSON_CFG2_LBT1 BIT(4)
78 #define LOONGSON_CFG2_LBT2 BIT(5)
79 #define LOONGSON_CFG2_LBT3 BIT(6)
80 #define LOONGSON_CFG2_LBTMMU BIT(7)
81 #define LOONGSON_CFG2_LPMP BIT(8)
82 #define LOONGSON_CFG2_LPMREV GENMASK(11, 9)
83 #define LOONGSON_CFG2_LAMO BIT(12)
84 #define LOONGSON_CFG2_LPIXU BIT(13)
85 #define LOONGSON_CFG2_LPIXNU BIT(14)
86 #define LOONGSON_CFG2_LVZP BIT(15)
87 #define LOONGSON_CFG2_LVZREV GENMASK(18, 16)
88 #define LOONGSON_CFG2_LGFTP BIT(19)
89 #define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20)
90 #define LOONGSON_CFG2_LLFTP BIT(23)
91 #define LOONGSON_CFG2_LLFTPREV GENMASK(26, 24)
92 #define LOONGSON_CFG2_LCSRP BIT(27)
93 #define LOONGSON_CFG2_LDISBLIKELY BIT(28)
94
95 #define LOONGSON_CFG2_LPMREV_OFFSET 9
96 #define LOONGSON_CFG2_LPM_REV1 (1 << LOONGSON_CFG2_LPMREV_OFFSET)
97 #define LOONGSON_CFG2_LPM_REV2 (2 << LOONGSON_CFG2_LPMREV_OFFSET)
98 #define LOONGSON_CFG2_LVZREV_OFFSET 16
99 #define LOONGSON_CFG2_LVZ_REV1 (1 << LOONGSON_CFG2_LVZREV_OFFSET)
100 #define LOONGSON_CFG2_LVZ_REV2 (2 << LOONGSON_CFG2_LVZREV_OFFSET)
101
102 #define LOONGSON_CFG3 0x3
103 #define LOONGSON_CFG3_LCAMP BIT(0)
104 #define LOONGSON_CFG3_LCAMREV GENMASK(3, 1)
105 #define LOONGSON_CFG3_LCAMNUM GENMASK(11, 4)
106 #define LOONGSON_CFG3_LCAMKW GENMASK(19, 12)
107 #define LOONGSON_CFG3_LCAMVW GENMASK(27, 20)
108
109 #define LOONGSON_CFG3_LCAMREV_OFFSET 1
110 #define LOONGSON_CFG3_LCAM_REV1 (1 << LOONGSON_CFG3_LCAMREV_OFFSET)
111 #define LOONGSON_CFG3_LCAM_REV2 (2 << LOONGSON_CFG3_LCAMREV_OFFSET)
112 #define LOONGSON_CFG3_LCAMNUM_OFFSET 4
113 #define LOONGSON_CFG3_LCAMNUM_REV1 (0x3f << LOONGSON_CFG3_LCAMNUM_OFFSET)
114 #define LOONGSON_CFG3_LCAMKW_OFFSET 12
115 #define LOONGSON_CFG3_LCAMKW_REV1 (0x27 << LOONGSON_CFG3_LCAMKW_OFFSET)
116 #define LOONGSON_CFG3_LCAMVW_OFFSET 20
117 #define LOONGSON_CFG3_LCAMVW_REV1 (0x3f << LOONGSON_CFG3_LCAMVW_OFFSET)
118
119 #define LOONGSON_CFG4 0x4
120 #define LOONGSON_CFG4_CCFREQ GENMASK(31, 0)
121
122 #define LOONGSON_CFG5 0x5
123 #define LOONGSON_CFG5_CFM GENMASK(15, 0)
124 #define LOONGSON_CFG5_CFD GENMASK(31, 16)
125
126 #define LOONGSON_CFG6 0x6
127
128 #define LOONGSON_CFG7 0x7
129 #define LOONGSON_CFG7_GCCAEQRP BIT(0)
130 #define LOONGSON_CFG7_UCAWINP BIT(1)
131
cpu_has_csr(void)132 static inline bool cpu_has_csr(void)
133 {
134 if (cpu_has_cfg())
135 return (read_cpucfg(LOONGSON_CFG2) & LOONGSON_CFG2_LCSRP);
136
137 return false;
138 }
139
csr_readl(u32 reg)140 static inline u32 csr_readl(u32 reg)
141 {
142 u32 __res;
143
144 /* RDCSR reg, val */
145 __asm__ __volatile__(
146 "parse_r __res,%0\n\t"
147 "parse_r reg,%1\n\t"
148 ".insn \n\t"
149 ".word (0xc8000118 | (reg << 21) | (__res << 11))\n\t"
150 :"=r"(__res)
151 :"r"(reg)
152 :
153 );
154 return __res;
155 }
156
csr_readq(u32 reg)157 static inline u64 csr_readq(u32 reg)
158 {
159 u64 __res;
160
161 /* DRDCSR reg, val */
162 __asm__ __volatile__(
163 "parse_r __res,%0\n\t"
164 "parse_r reg,%1\n\t"
165 ".insn \n\t"
166 ".word (0xc8020118 | (reg << 21) | (__res << 11))\n\t"
167 :"=r"(__res)
168 :"r"(reg)
169 :
170 );
171 return __res;
172 }
173
csr_writel(u32 val,u32 reg)174 static inline void csr_writel(u32 val, u32 reg)
175 {
176 /* WRCSR reg, val */
177 __asm__ __volatile__(
178 "parse_r reg,%0\n\t"
179 "parse_r val,%1\n\t"
180 ".insn \n\t"
181 ".word (0xc8010118 | (reg << 21) | (val << 11))\n\t"
182 :
183 :"r"(reg),"r"(val)
184 :
185 );
186 }
187
csr_writeq(u64 val,u32 reg)188 static inline void csr_writeq(u64 val, u32 reg)
189 {
190 /* DWRCSR reg, val */
191 __asm__ __volatile__(
192 "parse_r reg,%0\n\t"
193 "parse_r val,%1\n\t"
194 ".insn \n\t"
195 ".word (0xc8030118 | (reg << 21) | (val << 11))\n\t"
196 :
197 :"r"(reg),"r"(val)
198 :
199 );
200 }
201
202 /* Public CSR Register can also be accessed with regular addresses */
203 #define CSR_PUBLIC_MMIO_BASE 0x1fe00000
204
205 #define MMIO_CSR(x) (void *)TO_UNCAC(CSR_PUBLIC_MMIO_BASE + x)
206
207 #define LOONGSON_CSR_FEATURES 0x8
208 #define LOONGSON_CSRF_TEMP BIT(0)
209 #define LOONGSON_CSRF_NODECNT BIT(1)
210 #define LOONGSON_CSRF_MSI BIT(2)
211 #define LOONGSON_CSRF_EXTIOI BIT(3)
212 #define LOONGSON_CSRF_IPI BIT(4)
213 #define LOONGSON_CSRF_FREQ BIT(5)
214
215 #define LOONGSON_CSR_VENDOR 0x10 /* Vendor name string, should be "Loongson" */
216 #define LOONGSON_CSR_CPUNAME 0x20 /* Processor name string */
217 #define LOONGSON_CSR_NODECNT 0x408
218 #define LOONGSON_CSR_CPUTEMP 0x428
219
220 /* PerCore CSR, only accessable by local cores */
221 #define LOONGSON_CSR_IPI_STATUS 0x1000
222 #define LOONGSON_CSR_IPI_EN 0x1004
223 #define LOONGSON_CSR_IPI_SET 0x1008
224 #define LOONGSON_CSR_IPI_CLEAR 0x100c
225 #define LOONGSON_CSR_IPI_SEND 0x1040
226 #define CSR_IPI_SEND_IP_SHIFT 0
227 #define CSR_IPI_SEND_CPU_SHIFT 16
228 #define CSR_IPI_SEND_BLOCK BIT(31)
229
230 #define LOONGSON_CSR_MAIL_BUF0 0x1020
231 #define LOONGSON_CSR_MAIL_SEND 0x1048
232 #define CSR_MAIL_SEND_BLOCK BIT_ULL(31)
233 #define CSR_MAIL_SEND_BOX_LOW(box) (box << 1)
234 #define CSR_MAIL_SEND_BOX_HIGH(box) ((box << 1) + 1)
235 #define CSR_MAIL_SEND_BOX_SHIFT 2
236 #define CSR_MAIL_SEND_CPU_SHIFT 16
237 #define CSR_MAIL_SEND_BUF_SHIFT 32
238 #define CSR_MAIL_SEND_H32_MASK 0xFFFFFFFF00000000ULL
239
drdtime(void)240 static inline u64 drdtime(void)
241 {
242 int rID = 0;
243 u64 val = 0;
244
245 __asm__ __volatile__(
246 "parse_r rID,%0\n\t"
247 "parse_r val,%1\n\t"
248 ".insn \n\t"
249 ".word (0xc8090118 | (rID << 21) | (val << 11))\n\t"
250 :"=r"(rID),"=r"(val)
251 :
252 );
253 return val;
254 }
255
256 #endif
257
