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/Linux-v5.15/Documentation/admin-guide/hw-vuln/
Dl1d_flush.rst1 L1D Flushing
5 leaks from the Level 1 Data cache (L1D) the kernel provides an opt-in
6 mechanism to flush the L1D cache on context switch.
10 (snooping of) from the L1D cache.
34 When PR_SET_L1D_FLUSH is enabled for a task a flush of the L1D cache is
38 If the underlying CPU supports L1D flushing in hardware, the hardware
44 The kernel command line allows to control the L1D flush mitigations at boot
58 The mechanism does not mitigate L1D data leaks between tasks belonging to
66 **NOTE** : The opt-in of a task for L1D flushing works only when the task's
68 requested L1D flushing is scheduled on a SMT-enabled core the kernel sends
Dl1tf.rst97 share the L1 Data Cache (L1D) is important for this. As the flaw allows
98 only to attack data which is present in L1D, a malicious guest running
99 on one Hyperthread can attack the data which is brought into the L1D by
145 - L1D Flush mode:
148 'L1D vulnerable' L1D flushing is disabled
150 'L1D conditional cache flushes' L1D flush is conditionally enabled
152 'L1D cache flushes' L1D flush is unconditionally enabled
170 1. L1D flush on VMENTER
173 To make sure that a guest cannot attack data which is present in the L1D
174 the hypervisor flushes the L1D before entering the guest.
[all …]
Dmds.rst176 If the L1D flush mitigation is enabled and up to date microcode is
177 available, the L1D flush mitigation is automatically protecting the
180 If the L1D flush mitigation is disabled then the MDS mitigation is
/Linux-v5.15/arch/arm/kernel/
Dperf_event_v7.c179 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
180 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
181 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
182 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
229 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
230 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
231 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
232 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
266 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
267 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
[all …]
Dperf_event_v6.c96 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
97 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
99 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
159 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
160 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
161 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
162 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
Dperf_event_xscale.c73 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
74 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
75 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
76 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
/Linux-v5.15/arch/arm64/kernel/
Dperf_event.c60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
84 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
95 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
96 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
97 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
112 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
113 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
121 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
[all …]
/Linux-v5.15/arch/alpha/kernel/
Dsetup.c1280 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1290 L1D = L1I; in determine_cpu_caches()
1311 L1I = L1D = CSHAPE(8*1024, 5, 1); in determine_cpu_caches()
1326 L1I = L1D = CSHAPE(8*1024, 5, 1); in determine_cpu_caches()
1352 L1D = CSHAPE(8*1024, 5, 1); in determine_cpu_caches()
1355 L1D = CSHAPE(16*1024, 5, 1); in determine_cpu_caches()
1378 L1I = L1D = CSHAPE(64*1024, 6, 2); in determine_cpu_caches()
1385 L1I = L1D = CSHAPE(64*1024, 6, 2); in determine_cpu_caches()
1392 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1397 alpha_l1d_cacheshape = L1D; in determine_cpu_caches()
/Linux-v5.15/arch/powerpc/perf/
De6500-pmu.c36 [C(L1D)] = {
De500-pmu.c39 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
Dpower10-pmu.c348 [C(L1D)] = {
449 [C(L1D)] = {
Dmpc7450-pmu.c366 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
Dgeneric-compat-pmu.c176 [ C(L1D) ] = {
Dpower8-pmu.c257 [ C(L1D) ] = {
/Linux-v5.15/arch/mips/kernel/
Dperf_event_mipsxx.c1019 [C(L1D)] = {
1100 [C(L1D)] = {
1175 [C(L1D)] = {
1215 [C(L1D)] = {
1270 [C(L1D)] = {
1333 [C(L1D)] = {
1386 [C(L1D)] = {
1444 [C(L1D)] = {
1484 [C(L1D)] = {
/Linux-v5.15/arch/arc/include/asm/
Dperf_event.h127 [C(L1D)] = {
/Linux-v5.15/arch/sh/kernel/cpu/sh4a/
Dperf_event.c116 [ C(L1D) ] = {
/Linux-v5.15/arch/x86/events/intel/
Dp6.c28 [ C(L1D) ] = {
Dknc.c26 [ C(L1D) ] = {
/Linux-v5.15/arch/sh/kernel/cpu/sh4/
Dperf_event.c91 [ C(L1D) ] = {
/Linux-v5.15/arch/x86/events/zhaoxin/
Dcore.c51 [C(L1D)] = {
155 [C(L1D)] = {
/Linux-v5.15/Documentation/userspace-api/
Dspec_ctrl.rst110 - PR_SPEC_L1D_FLUSH: Flush L1D Cache on context switch out of the task
/Linux-v5.15/arch/x86/events/amd/
Dcore.c26 [ C(L1D) ] = {
130 [C(L1D)] = {
/Linux-v5.15/arch/sparc/kernel/
Dperf_event.c221 [C(L1D)] = {
359 [C(L1D)] = {
494 [C(L1D)] = {
631 [C(L1D)] = {
/Linux-v5.15/arch/nds32/include/asm/
Dpmu.h244 [C(L1D)] = {

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