Searched refs:IS_FPGA_MAXIMUS_DC (Results 1 – 25 of 36) sorted by relevance
12
67 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_translate_init()
69 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_factory_init()
114 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dce112_set_clock()156 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dce112_set_dispclk()
123 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce112_enable_display_power_gating()
135 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in rv1_vbios_smu_set_dispclk()
421 if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) in dp_set_dsc_on_rx()471 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()498 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()
79 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn31_init_hw()131 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn31_init_hw()530 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn31_reset_back_end_for_pipe()
146 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn31_hw_sequencer_construct()
142 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn20_hw_sequencer_construct()
162 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce120_enable_display_power_gating()
148 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn21_hw_sequencer_construct()
1965 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) in dcn21_resource_construct()2251 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in dcn21_resource_construct()
146 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_hw_sequencer_construct()
451 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_init_hw()495 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_init_hw()
131 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in rn_vbios_smu_set_dispclk()
957 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in rn_clk_mgr_construct()1018 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) { in rn_clk_mgr_construct()
72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ macro76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
488 !IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()500 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()
542 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn20_clk_mgr_construct()
913 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_reset_back_end_for_pipe()1320 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()1351 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()2899 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_prepare_bandwidth()2932 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_optimize_bandwidth()
551 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn3_clk_mgr_construct()
669 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn31_clk_mgr_construct()
775 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in vg_clk_mgr_construct()
331 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dce112_set_clock()
1100 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn21_dmcu_construct()