1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * ipac.h Defines for the Infineon (former Siemens) ISDN 5 * chip series 6 * 7 * Author Karsten Keil <keil@isdn4linux.de> 8 * 9 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> 10 */ 11 12 #include "iohelper.h" 13 14 struct isac_hw { 15 struct dchannel dch; 16 u32 type; 17 u32 off; /* offset to isac regs */ 18 char *name; 19 spinlock_t *hwlock; /* lock HW access */ 20 read_reg_func *read_reg; 21 write_reg_func *write_reg; 22 fifo_func *read_fifo; 23 fifo_func *write_fifo; 24 int (*monitor)(void *, u32, u8 *, int); 25 void (*release)(struct isac_hw *); 26 int (*init)(struct isac_hw *); 27 int (*ctrl)(struct isac_hw *, u32, u_long); 28 int (*open)(struct isac_hw *, struct channel_req *); 29 u8 *mon_tx; 30 u8 *mon_rx; 31 int mon_txp; 32 int mon_txc; 33 int mon_rxp; 34 struct arcofi_msg *arcofi_list; 35 struct timer_list arcofitimer; 36 wait_queue_head_t arcofi_wait; 37 u8 arcofi_bc; 38 u8 arcofi_state; 39 u8 mocr; 40 u8 adf2; 41 u8 state; 42 }; 43 44 struct ipac_hw; 45 46 struct hscx_hw { 47 struct bchannel bch; 48 struct ipac_hw *ip; 49 u8 fifo_size; 50 u8 off; /* offset to ICA or ICB */ 51 u8 slot; 52 char log[64]; 53 }; 54 55 struct ipac_hw { 56 struct isac_hw isac; 57 struct hscx_hw hscx[2]; 58 char *name; 59 void *hw; 60 spinlock_t *hwlock; /* lock HW access */ 61 struct module *owner; 62 u32 type; 63 read_reg_func *read_reg; 64 write_reg_func *write_reg; 65 fifo_func *read_fifo; 66 fifo_func *write_fifo; 67 void (*release)(struct ipac_hw *); 68 int (*init)(struct ipac_hw *); 69 int (*ctrl)(struct ipac_hw *, u32, u_long); 70 u8 conf; 71 }; 72 73 #define IPAC_TYPE_ISAC 0x0010 74 #define IPAC_TYPE_IPAC 0x0020 75 #define IPAC_TYPE_ISACX 0x0040 76 #define IPAC_TYPE_IPACX 0x0080 77 #define IPAC_TYPE_HSCX 0x0100 78 79 #define ISAC_USE_ARCOFI 0x1000 80 81 /* Monitor functions */ 82 #define MONITOR_RX_0 0x1000 83 #define MONITOR_RX_1 0x1001 84 #define MONITOR_TX_0 0x2000 85 #define MONITOR_TX_1 0x2001 86 87 /* All registers original Siemens Spec */ 88 /* IPAC/ISAC registers */ 89 #define ISAC_ISTA 0x20 90 #define ISAC_MASK 0x20 91 #define ISAC_CMDR 0x21 92 #define ISAC_STAR 0x21 93 #define ISAC_MODE 0x22 94 #define ISAC_TIMR 0x23 95 #define ISAC_EXIR 0x24 96 #define ISAC_RBCL 0x25 97 #define ISAC_RSTA 0x27 98 #define ISAC_RBCH 0x2A 99 #define ISAC_SPCR 0x30 100 #define ISAC_CIR0 0x31 101 #define ISAC_CIX0 0x31 102 #define ISAC_MOR0 0x32 103 #define ISAC_MOX0 0x32 104 #define ISAC_CIR1 0x33 105 #define ISAC_CIX1 0x33 106 #define ISAC_MOR1 0x34 107 #define ISAC_MOX1 0x34 108 #define ISAC_STCR 0x37 109 #define ISAC_ADF1 0x38 110 #define ISAC_ADF2 0x39 111 #define ISAC_MOCR 0x3a 112 #define ISAC_MOSR 0x3a 113 #define ISAC_SQRR 0x3b 114 #define ISAC_SQXR 0x3b 115 116 #define ISAC_RBCH_XAC 0x80 117 118 #define IPAC_D_TIN2 0x01 119 120 /* IPAC/HSCX */ 121 #define IPAC_ISTAB 0x20 /* RD */ 122 #define IPAC_MASKB 0x20 /* WR */ 123 #define IPAC_STARB 0x21 /* RD */ 124 #define IPAC_CMDRB 0x21 /* WR */ 125 #define IPAC_MODEB 0x22 /* R/W */ 126 #define IPAC_EXIRB 0x24 /* RD */ 127 #define IPAC_RBCLB 0x25 /* RD */ 128 #define IPAC_RAH1 0x26 /* WR */ 129 #define IPAC_RAH2 0x27 /* WR */ 130 #define IPAC_RSTAB 0x27 /* RD */ 131 #define IPAC_RAL1 0x28 /* R/W */ 132 #define IPAC_RAL2 0x29 /* WR */ 133 #define IPAC_RHCRB 0x29 /* RD */ 134 #define IPAC_XBCL 0x2A /* WR */ 135 #define IPAC_CCR2 0x2C /* R/W */ 136 #define IPAC_RBCHB 0x2D /* RD */ 137 #define IPAC_XBCH 0x2D /* WR */ 138 #define HSCX_VSTR 0x2E /* RD */ 139 #define IPAC_RLCR 0x2E /* WR */ 140 #define IPAC_CCR1 0x2F /* R/W */ 141 #define IPAC_TSAX 0x30 /* WR */ 142 #define IPAC_TSAR 0x31 /* WR */ 143 #define IPAC_XCCR 0x32 /* WR */ 144 #define IPAC_RCCR 0x33 /* WR */ 145 146 /* IPAC_ISTAB/IPAC_MASKB bits */ 147 #define IPAC_B_XPR 0x10 148 #define IPAC_B_RPF 0x40 149 #define IPAC_B_RME 0x80 150 #define IPAC_B_ON 0x2F 151 152 /* IPAC_EXIRB bits */ 153 #define IPAC_B_RFS 0x04 154 #define IPAC_B_RFO 0x10 155 #define IPAC_B_XDU 0x40 156 #define IPAC_B_XMR 0x80 157 158 /* IPAC special registers */ 159 #define IPAC_CONF 0xC0 /* R/W */ 160 #define IPAC_ISTA 0xC1 /* RD */ 161 #define IPAC_MASK 0xC1 /* WR */ 162 #define IPAC_ID 0xC2 /* RD */ 163 #define IPAC_ACFG 0xC3 /* R/W */ 164 #define IPAC_AOE 0xC4 /* R/W */ 165 #define IPAC_ARX 0xC5 /* RD */ 166 #define IPAC_ATX 0xC5 /* WR */ 167 #define IPAC_PITA1 0xC6 /* R/W */ 168 #define IPAC_PITA2 0xC7 /* R/W */ 169 #define IPAC_POTA1 0xC8 /* R/W */ 170 #define IPAC_POTA2 0xC9 /* R/W */ 171 #define IPAC_PCFG 0xCA /* R/W */ 172 #define IPAC_SCFG 0xCB /* R/W */ 173 #define IPAC_TIMR2 0xCC /* R/W */ 174 175 /* IPAC_ISTA/_MASK bits */ 176 #define IPAC__EXB 0x01 177 #define IPAC__ICB 0x02 178 #define IPAC__EXA 0x04 179 #define IPAC__ICA 0x08 180 #define IPAC__EXD 0x10 181 #define IPAC__ICD 0x20 182 #define IPAC__INT0 0x40 183 #define IPAC__INT1 0x80 184 #define IPAC__ON 0xC0 185 186 /* HSCX ISTA/MASK bits */ 187 #define HSCX__EXB 0x01 188 #define HSCX__EXA 0x02 189 #define HSCX__ICA 0x04 190 191 /* ISAC/ISACX/IPAC/IPACX L1 commands */ 192 #define ISAC_CMD_TIM 0x0 193 #define ISAC_CMD_RS 0x1 194 #define ISAC_CMD_SCZ 0x4 195 #define ISAC_CMD_SSZ 0x2 196 #define ISAC_CMD_AR8 0x8 197 #define ISAC_CMD_AR10 0x9 198 #define ISAC_CMD_ARL 0xA 199 #define ISAC_CMD_DUI 0xF 200 201 /* ISAC/ISACX/IPAC/IPACX L1 indications */ 202 #define ISAC_IND_DR 0x0 203 #define ISAC_IND_RS 0x1 204 #define ISAC_IND_SD 0x2 205 #define ISAC_IND_DIS 0x3 206 #define ISAC_IND_RSY 0x4 207 #define ISAC_IND_DR6 0x5 208 #define ISAC_IND_EI 0x6 209 #define ISAC_IND_PU 0x7 210 #define ISAC_IND_ARD 0x8 211 #define ISAC_IND_TI 0xA 212 #define ISAC_IND_ATI 0xB 213 #define ISAC_IND_AI8 0xC 214 #define ISAC_IND_AI10 0xD 215 #define ISAC_IND_DID 0xF 216 217 /* the new ISACX / IPACX */ 218 /* D-channel registers */ 219 #define ISACX_RFIFOD 0x00 /* RD */ 220 #define ISACX_XFIFOD 0x00 /* WR */ 221 #define ISACX_ISTAD 0x20 /* RD */ 222 #define ISACX_MASKD 0x20 /* WR */ 223 #define ISACX_STARD 0x21 /* RD */ 224 #define ISACX_CMDRD 0x21 /* WR */ 225 #define ISACX_MODED 0x22 /* R/W */ 226 #define ISACX_EXMD1 0x23 /* R/W */ 227 #define ISACX_TIMR1 0x24 /* R/W */ 228 #define ISACX_SAP1 0x25 /* WR */ 229 #define ISACX_SAP2 0x26 /* WR */ 230 #define ISACX_RBCLD 0x26 /* RD */ 231 #define ISACX_RBCHD 0x27 /* RD */ 232 #define ISACX_TEI1 0x27 /* WR */ 233 #define ISACX_TEI2 0x28 /* WR */ 234 #define ISACX_RSTAD 0x28 /* RD */ 235 #define ISACX_TMD 0x29 /* R/W */ 236 #define ISACX_CIR0 0x2E /* RD */ 237 #define ISACX_CIX0 0x2E /* WR */ 238 #define ISACX_CIR1 0x2F /* RD */ 239 #define ISACX_CIX1 0x2F /* WR */ 240 241 /* Transceiver registers */ 242 #define ISACX_TR_CONF0 0x30 /* R/W */ 243 #define ISACX_TR_CONF1 0x31 /* R/W */ 244 #define ISACX_TR_CONF2 0x32 /* R/W */ 245 #define ISACX_TR_STA 0x33 /* RD */ 246 #define ISACX_TR_CMD 0x34 /* R/W */ 247 #define ISACX_SQRR1 0x35 /* RD */ 248 #define ISACX_SQXR1 0x35 /* WR */ 249 #define ISACX_SQRR2 0x36 /* RD */ 250 #define ISACX_SQXR2 0x36 /* WR */ 251 #define ISACX_SQRR3 0x37 /* RD */ 252 #define ISACX_SQXR3 0x37 /* WR */ 253 #define ISACX_ISTATR 0x38 /* RD */ 254 #define ISACX_MASKTR 0x39 /* R/W */ 255 #define ISACX_TR_MODE 0x3A /* R/W */ 256 #define ISACX_ACFG1 0x3C /* R/W */ 257 #define ISACX_ACFG2 0x3D /* R/W */ 258 #define ISACX_AOE 0x3E /* R/W */ 259 #define ISACX_ARX 0x3F /* RD */ 260 #define ISACX_ATX 0x3F /* WR */ 261 262 /* IOM: Timeslot, DPS, CDA */ 263 #define ISACX_CDA10 0x40 /* R/W */ 264 #define ISACX_CDA11 0x41 /* R/W */ 265 #define ISACX_CDA20 0x42 /* R/W */ 266 #define ISACX_CDA21 0x43 /* R/W */ 267 #define ISACX_CDA_TSDP10 0x44 /* R/W */ 268 #define ISACX_CDA_TSDP11 0x45 /* R/W */ 269 #define ISACX_CDA_TSDP20 0x46 /* R/W */ 270 #define ISACX_CDA_TSDP21 0x47 /* R/W */ 271 #define ISACX_BCHA_TSDP_BC1 0x48 /* R/W */ 272 #define ISACX_BCHA_TSDP_BC2 0x49 /* R/W */ 273 #define ISACX_BCHB_TSDP_BC1 0x4A /* R/W */ 274 #define ISACX_BCHB_TSDP_BC2 0x4B /* R/W */ 275 #define ISACX_TR_TSDP_BC1 0x4C /* R/W */ 276 #define ISACX_TR_TSDP_BC2 0x4D /* R/W */ 277 #define ISACX_CDA1_CR 0x4E /* R/W */ 278 #define ISACX_CDA2_CR 0x4F /* R/W */ 279 280 /* IOM: Contol, Sync transfer, Monitor */ 281 #define ISACX_TR_CR 0x50 /* R/W */ 282 #define ISACX_TRC_CR 0x50 /* R/W */ 283 #define ISACX_BCHA_CR 0x51 /* R/W */ 284 #define ISACX_BCHB_CR 0x52 /* R/W */ 285 #define ISACX_DCI_CR 0x53 /* R/W */ 286 #define ISACX_DCIC_CR 0x53 /* R/W */ 287 #define ISACX_MON_CR 0x54 /* R/W */ 288 #define ISACX_SDS1_CR 0x55 /* R/W */ 289 #define ISACX_SDS2_CR 0x56 /* R/W */ 290 #define ISACX_IOM_CR 0x57 /* R/W */ 291 #define ISACX_STI 0x58 /* RD */ 292 #define ISACX_ASTI 0x58 /* WR */ 293 #define ISACX_MSTI 0x59 /* R/W */ 294 #define ISACX_SDS_CONF 0x5A /* R/W */ 295 #define ISACX_MCDA 0x5B /* RD */ 296 #define ISACX_MOR 0x5C /* RD */ 297 #define ISACX_MOX 0x5C /* WR */ 298 #define ISACX_MOSR 0x5D /* RD */ 299 #define ISACX_MOCR 0x5E /* R/W */ 300 #define ISACX_MSTA 0x5F /* RD */ 301 #define ISACX_MCONF 0x5F /* WR */ 302 303 /* Interrupt and general registers */ 304 #define ISACX_ISTA 0x60 /* RD */ 305 #define ISACX_MASK 0x60 /* WR */ 306 #define ISACX_AUXI 0x61 /* RD */ 307 #define ISACX_AUXM 0x61 /* WR */ 308 #define ISACX_MODE1 0x62 /* R/W */ 309 #define ISACX_MODE2 0x63 /* R/W */ 310 #define ISACX_ID 0x64 /* RD */ 311 #define ISACX_SRES 0x64 /* WR */ 312 #define ISACX_TIMR2 0x65 /* R/W */ 313 314 /* Register Bits */ 315 /* ISACX/IPACX _ISTAD (R) and _MASKD (W) */ 316 #define ISACX_D_XDU 0x04 317 #define ISACX_D_XMR 0x08 318 #define ISACX_D_XPR 0x10 319 #define ISACX_D_RFO 0x20 320 #define ISACX_D_RPF 0x40 321 #define ISACX_D_RME 0x80 322 323 /* ISACX/IPACX _ISTA (R) and _MASK (W) */ 324 #define ISACX__ICD 0x01 325 #define ISACX__MOS 0x02 326 #define ISACX__TRAN 0x04 327 #define ISACX__AUX 0x08 328 #define ISACX__CIC 0x10 329 #define ISACX__ST 0x20 330 #define IPACX__ON 0x2C 331 #define IPACX__ICB 0x40 332 #define IPACX__ICA 0x80 333 334 /* ISACX/IPACX _CMDRD (W) */ 335 #define ISACX_CMDRD_XRES 0x01 336 #define ISACX_CMDRD_XME 0x02 337 #define ISACX_CMDRD_XTF 0x08 338 #define ISACX_CMDRD_STI 0x10 339 #define ISACX_CMDRD_RRES 0x40 340 #define ISACX_CMDRD_RMC 0x80 341 342 /* ISACX/IPACX _RSTAD (R) */ 343 #define ISACX_RSTAD_TA 0x01 344 #define ISACX_RSTAD_CR 0x02 345 #define ISACX_RSTAD_SA0 0x04 346 #define ISACX_RSTAD_SA1 0x08 347 #define ISACX_RSTAD_RAB 0x10 348 #define ISACX_RSTAD_CRC 0x20 349 #define ISACX_RSTAD_RDO 0x40 350 #define ISACX_RSTAD_VFR 0x80 351 352 /* ISACX/IPACX _CIR0 (R) */ 353 #define ISACX_CIR0_BAS 0x01 354 #define ISACX_CIR0_SG 0x08 355 #define ISACX_CIR0_CIC1 0x08 356 #define ISACX_CIR0_CIC0 0x08 357 358 /* B-channel registers */ 359 #define IPACX_OFF_ICA 0x70 360 #define IPACX_OFF_ICB 0x80 361 362 /* ICA: IPACX_OFF_ICA + Reg ICB: IPACX_OFF_ICB + Reg */ 363 364 #define IPACX_ISTAB 0x00 /* RD */ 365 #define IPACX_MASKB 0x00 /* WR */ 366 #define IPACX_STARB 0x01 /* RD */ 367 #define IPACX_CMDRB 0x01 /* WR */ 368 #define IPACX_MODEB 0x02 /* R/W */ 369 #define IPACX_EXMB 0x03 /* R/W */ 370 #define IPACX_RAH1 0x05 /* WR */ 371 #define IPACX_RAH2 0x06 /* WR */ 372 #define IPACX_RBCLB 0x06 /* RD */ 373 #define IPACX_RBCHB 0x07 /* RD */ 374 #define IPACX_RAL1 0x07 /* WR */ 375 #define IPACX_RAL2 0x08 /* WR */ 376 #define IPACX_RSTAB 0x08 /* RD */ 377 #define IPACX_TMB 0x09 /* R/W */ 378 #define IPACX_RFIFOB 0x0A /* RD */ 379 #define IPACX_XFIFOB 0x0A /* WR */ 380 381 /* IPACX_ISTAB / IPACX_MASKB bits */ 382 #define IPACX_B_XDU 0x04 383 #define IPACX_B_XPR 0x10 384 #define IPACX_B_RFO 0x20 385 #define IPACX_B_RPF 0x40 386 #define IPACX_B_RME 0x80 387 388 #define IPACX_B_ON 0x0B 389 390 extern int mISDNisac_init(struct isac_hw *, void *); 391 extern irqreturn_t mISDNisac_irq(struct isac_hw *, u8); 392 extern u32 mISDNipac_init(struct ipac_hw *, void *); 393 extern irqreturn_t mISDNipac_irq(struct ipac_hw *, int); 394
