1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Intel IOP32X and IOP33X register definitions
4 *
5 * Author: Rory Bolt <rorybolt@pacbell.net>
6 * Copyright (C) 2002 Rory Bolt
7 * Copyright (C) 2004 Intel Corp.
8 */
9
10 #ifndef __IOP3XX_H
11 #define __IOP3XX_H
12
13 /*
14 * Peripherals that are shared between the iop32x and iop33x but
15 * located at different addresses.
16 */
17 #define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
18
19 #include "iop3xx.h"
20
21 /* ATU Parameters
22 * set up a 1:1 bus to physical ram relationship
23 * w/ physical ram on top of pci in the memory map
24 */
25 #define IOP32X_MAX_RAM_SIZE 0x40000000UL
26 #define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE
27 #define IOP3XX_PCI_LOWER_MEM_BA 0x80000000
28
29 /*
30 * IOP3XX GPIO handling
31 */
32 #define IOP3XX_GPIO_LINE(x) (x)
33
34 #ifndef __ASSEMBLY__
35 extern int init_atu;
36 extern int iop3xx_get_init_atu(void);
37 #endif
38
39
40 /*
41 * IOP3XX processor registers
42 */
43 #define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
44 #define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
45 #define IOP3XX_PERIPHERAL_SIZE 0x00002000
46 #define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
47 IOP3XX_PERIPHERAL_SIZE - 1)
48 #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
49 IOP3XX_PERIPHERAL_SIZE - 1)
50 #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
51 (IOP3XX_PERIPHERAL_PHYS_BASE\
52 - IOP3XX_PERIPHERAL_VIRT_BASE))
53 #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
54
55 /* Address Translation Unit */
56 #define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
57 #define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
58 #define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
59 #define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
60 #define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
61 #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
62 #define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
63 #define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
64 #define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
65 #define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
66 #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
67 #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
68 #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
69 #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
70 #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
71 #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
72 #define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
73 #define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
74 #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
75 #define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
76 #define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
77 #define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
78 #define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
79 #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
80 #define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
81 #define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
82 #define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
83 #define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
84 #define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
85 #define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
86 #define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
87 #define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
88 #define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
89 #define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
90 #define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
91 #define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
92 #define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
93 #define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
94 #define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
95 #define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
96 #define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
97 #define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
98 #define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
99 #define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
100 #define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
101 #define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
102 #define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
103 #define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
104 #define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
105 #define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
106 #define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
107 #define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
108 #define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
109 #define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
110 #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
111 #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
112 #define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
113 #define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
114 #define IOP3XX_ATUCR_OUT_EN (1 << 1)
115
116 #define IOP3XX_INIT_ATU_DEFAULT 0
117 #define IOP3XX_INIT_ATU_DISABLE -1
118 #define IOP3XX_INIT_ATU_ENABLE 1
119
120 /* Messaging Unit */
121 #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
122 #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
123 #define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
124 #define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
125 #define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
126 #define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
127 #define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
128 #define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
129 #define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
130 #define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
131 #define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
132 #define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
133 #define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
134 #define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
135 #define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
136 #define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
137 #define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
138 #define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
139 #define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
140 #define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
141 #define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
142
143 /* DMA Controller */
144 #define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
145 (0x400 + (chan << 6)))
146 #define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
147
148 /* Peripheral bus interface */
149 #define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
150 #define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
151 #define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
152 #define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
153 #define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
154 #define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
155 #define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
156 #define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
157 #define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
158 #define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
159 #define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
160 #define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
161 #define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
162 #define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
163 #define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
164 #define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
165 #define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
166
167 /* Peripheral performance monitoring unit */
168 #define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
169 #define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
170 #define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
171 #define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
172 /* PERCR0 DOESN'T EXIST - index from 1! */
173 #define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
174
175 /* Timers */
176 #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
177 #define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
178 #define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
179 #define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
180 #define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
181 #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
182 #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
183 #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
184 #define IOP_TMR_EN 0x02
185 #define IOP_TMR_RELOAD 0x04
186 #define IOP_TMR_PRIVILEGED 0x08
187 #define IOP_TMR_RATIO_1_1 0x00
188
189 /* Watchdog timer definitions */
190 #define IOP_WDTCR_EN_ARM 0x1e1e1e1e
191 #define IOP_WDTCR_EN 0xe1e1e1e1
192 /* iop3xx does not support stopping the watchdog, so we just re-arm */
193 #define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
194 #define IOP_WDTCR_DIS (IOP_WDTCR_EN)
195
196 /* Application accelerator unit */
197 #define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
198 #define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
199
200 /* I2C bus interface unit */
201 #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
202 #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
203 #define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
204 #define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
205 #define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
206 #define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
207 #define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
208 #define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
209 #define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
210 #define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
211
212
213 /*
214 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
215 */
216 #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
217 #define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000
218
219 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000
220 #define IOP3XX_PCI_LOWER_IO_BA 0x00000000
221
222 #ifndef __ASSEMBLY__
223
224 #include <linux/types.h>
225 #include <linux/reboot.h>
226
227 void iop3xx_map_io(void);
228 void iop_init_cp6_handler(void);
229 void iop_init_time(unsigned long tickrate);
230 void iop3xx_restart(enum reboot_mode, const char *);
231
read_tmr0(void)232 static inline u32 read_tmr0(void)
233 {
234 u32 val;
235 asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
236 return val;
237 }
238
write_tmr0(u32 val)239 static inline void write_tmr0(u32 val)
240 {
241 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
242 }
243
write_tmr1(u32 val)244 static inline void write_tmr1(u32 val)
245 {
246 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
247 }
248
read_tcr0(void)249 static inline u32 read_tcr0(void)
250 {
251 u32 val;
252 asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
253 return val;
254 }
255
write_tcr0(u32 val)256 static inline void write_tcr0(u32 val)
257 {
258 asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
259 }
260
read_tcr1(void)261 static inline u32 read_tcr1(void)
262 {
263 u32 val;
264 asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
265 return val;
266 }
267
write_tcr1(u32 val)268 static inline void write_tcr1(u32 val)
269 {
270 asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
271 }
272
write_trr0(u32 val)273 static inline void write_trr0(u32 val)
274 {
275 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
276 }
277
write_trr1(u32 val)278 static inline void write_trr1(u32 val)
279 {
280 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
281 }
282
write_tisr(u32 val)283 static inline void write_tisr(u32 val)
284 {
285 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
286 }
287
read_wdtcr(void)288 static inline u32 read_wdtcr(void)
289 {
290 u32 val;
291 asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
292 return val;
293 }
write_wdtcr(u32 val)294 static inline void write_wdtcr(u32 val)
295 {
296 asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
297 }
298
299 extern unsigned long get_iop_tick_rate(void);
300
301 /* only iop13xx has these registers, we define these to present a
302 * common register interface for the iop_wdt driver.
303 */
304 #define IOP_RCSR_WDT (0)
read_rcsr(void)305 static inline u32 read_rcsr(void)
306 {
307 return 0;
308 }
write_wdtsr(u32 val)309 static inline void write_wdtsr(u32 val)
310 {
311 do { } while (0);
312 }
313
314 extern struct platform_device iop3xx_dma_0_channel;
315 extern struct platform_device iop3xx_dma_1_channel;
316 extern struct platform_device iop3xx_aau_channel;
317 extern struct platform_device iop3xx_i2c0_device;
318 extern struct platform_device iop3xx_i2c1_device;
319 extern struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup;
320 extern struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup;
321
322 #endif
323
324
325 #endif
326
