Searched refs:INTx (Results 1 – 14 of 14) sorted by relevance
20 protocol describes this in-band legacy wire-interrupt INTx mechanism for22 describe problems with the Core IO handling of INTx message routing to the29 When in-band legacy INTx messages are forwarded to the PCH, they in turn103 When this bit is set. Local INTx messages received from the110 has been to make use of PCI Interrupt pin to INTx routing tables for112 line by default. Therefore, on chipsets where this INTx routing cannot be147 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt
14 INTx interrupts (using _PRT).21 or if the device has INTx interrupts connected by platform interrupt
341 legacy INTx should chose the right one based on the msi_enabled
17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
33 The core provides a single interrupt for both INTx/MSI messages. So,36 the four INTx interrupts in ISR and route them to this domain.
66 The core controller provides a single interrupt for legacy INTx. The PCIe node69 INTx interrupts are decoded and routed.
22 List of devices which can have interrupt control flag (INTx,
28 …tus: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
358 <TAbort- <MAbort- >SERR- <PERR- INTx-
784 INTx, enumerator
12036 phba->intr_type = INTx; in lpfc_sli_enable_intr()13031 phba->intr_type = INTx; in lpfc_sli4_enable_intr()
538 if ((q->phba->intr_type == INTx) && (arm == LPFC_QUEUE_REARM)) in lpfc_sli4_write_eq_db()571 if ((q->phba->intr_type == INTx) && (arm == LPFC_QUEUE_REARM)) in lpfc_sli4_if6_write_eq_db()
1086 Some chipsets generate a legacy INTx "boot IRQ" when the IRQ
4080 all PCIe root ports use INTx for all services).
