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Searched refs:INTRL2_CPU_CLEAR (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.15/drivers/net/dsa/
Dbcm_sf2.c229 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); in bcm_sf2_port_intr_disable()
237 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); in bcm_sf2_port_intr_disable()
407 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); in bcm_sf2_switch_0_isr()
419 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); in bcm_sf2_switch_1_isr()
509 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); in bcm_sf2_intr_disable()
511 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); in bcm_sf2_intr_disable()
Dbcm_sf2_regs.h83 #define INTRL2_CPU_CLEAR 0x08 macro
/Linux-v5.15/drivers/net/ethernet/broadcom/
Dbcmsysport.c759 intrl2_0_writel(priv, INTRL2_0_RDMA_MBDONE, INTRL2_CPU_CLEAR); in bcm_sysport_desc_rx()
912 intrl2_1_writel(ring->priv, BIT(ring->index), INTRL2_CPU_CLEAR); in __bcm_sysport_tx_reclaim()
915 INTRL2_0_TDMA_MBDONE_SHIFT), INTRL2_CPU_CLEAR); in __bcm_sysport_tx_reclaim()
1136 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); in bcm_sysport_rx_isr()
1187 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); in bcm_sysport_tx_isr()
1927 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); in bcm_sysport_mask_all_intrs()
1930 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); in bcm_sysport_mask_all_intrs()
Dbcmsysport.h113 #define INTRL2_CPU_CLEAR 0x08 macro
/Linux-v5.15/drivers/net/ethernet/broadcom/genet/
Dbcmgenet.c1838 INTRL2_CPU_CLEAR); in __bcmgenet_tx_reclaim()
1841 INTRL2_CPU_CLEAR); in __bcmgenet_tx_reclaim()
2198 INTRL2_CPU_CLEAR); in bcmgenet_desc_rx()
2203 INTRL2_CPU_CLEAR); in bcmgenet_desc_rx()
2442 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); in bcmgenet_intr_disable()
2444 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); in bcmgenet_intr_disable()
3095 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); in bcmgenet_isr1()
3144 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); in bcmgenet_isr0()
4133 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR); in bcmgenet_resume_noirq()
Dbcmgenet.h240 #define INTRL2_CPU_CLEAR 0x08 macro