1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPMC support functions
4 *
5 * Copyright (C) 2005-2006 Nokia Corporation
6 *
7 * Author: Juha Yrjola
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 */
12 #include <linux/cpu_pm.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/ioport.h>
19 #include <linux/spinlock.h>
20 #include <linux/io.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
23 #include <linux/gpio/machine.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
26 #include <linux/platform_device.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_platform.h>
31 #include <linux/omap-gpmc.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/sizes.h>
34
35 #include <linux/platform_data/mtd-nand-omap2.h>
36
37 #define DEVICE_NAME "omap-gpmc"
38
39 /* GPMC register offsets */
40 #define GPMC_REVISION 0x00
41 #define GPMC_SYSCONFIG 0x10
42 #define GPMC_SYSSTATUS 0x14
43 #define GPMC_IRQSTATUS 0x18
44 #define GPMC_IRQENABLE 0x1c
45 #define GPMC_TIMEOUT_CONTROL 0x40
46 #define GPMC_ERR_ADDRESS 0x44
47 #define GPMC_ERR_TYPE 0x48
48 #define GPMC_CONFIG 0x50
49 #define GPMC_STATUS 0x54
50 #define GPMC_PREFETCH_CONFIG1 0x1e0
51 #define GPMC_PREFETCH_CONFIG2 0x1e4
52 #define GPMC_PREFETCH_CONTROL 0x1ec
53 #define GPMC_PREFETCH_STATUS 0x1f0
54 #define GPMC_ECC_CONFIG 0x1f4
55 #define GPMC_ECC_CONTROL 0x1f8
56 #define GPMC_ECC_SIZE_CONFIG 0x1fc
57 #define GPMC_ECC1_RESULT 0x200
58 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
59 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
60 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
61 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
65
66 /* GPMC ECC control settings */
67 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
68 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
69 #define GPMC_ECC_CTRL_ECCREG1 0x001
70 #define GPMC_ECC_CTRL_ECCREG2 0x002
71 #define GPMC_ECC_CTRL_ECCREG3 0x003
72 #define GPMC_ECC_CTRL_ECCREG4 0x004
73 #define GPMC_ECC_CTRL_ECCREG5 0x005
74 #define GPMC_ECC_CTRL_ECCREG6 0x006
75 #define GPMC_ECC_CTRL_ECCREG7 0x007
76 #define GPMC_ECC_CTRL_ECCREG8 0x008
77 #define GPMC_ECC_CTRL_ECCREG9 0x009
78
79 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
80
81 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
82
83 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
84 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
85 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
87 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
88 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
89
90 #define GPMC_CS0_OFFSET 0x60
91 #define GPMC_CS_SIZE 0x30
92 #define GPMC_BCH_SIZE 0x10
93
94 /*
95 * The first 1MB of GPMC address space is typically mapped to
96 * the internal ROM. Never allocate the first page, to
97 * facilitate bug detection; even if we didn't boot from ROM.
98 * As GPMC minimum partition size is 16MB we can only start from
99 * there.
100 */
101 #define GPMC_MEM_START 0x1000000
102 #define GPMC_MEM_END 0x3FFFFFFF
103
104 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
105 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
106
107 #define CS_NUM_SHIFT 24
108 #define ENABLE_PREFETCH (0x1 << 7)
109 #define DMA_MPU_MODE 2
110
111 #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
112 #define GPMC_REVISION_MINOR(l) ((l) & 0xf)
113
114 #define GPMC_HAS_WR_ACCESS 0x1
115 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
116 #define GPMC_HAS_MUX_AAD 0x4
117
118 #define GPMC_NR_WAITPINS 4
119
120 #define GPMC_CS_CONFIG1 0x00
121 #define GPMC_CS_CONFIG2 0x04
122 #define GPMC_CS_CONFIG3 0x08
123 #define GPMC_CS_CONFIG4 0x0c
124 #define GPMC_CS_CONFIG5 0x10
125 #define GPMC_CS_CONFIG6 0x14
126 #define GPMC_CS_CONFIG7 0x18
127 #define GPMC_CS_NAND_COMMAND 0x1c
128 #define GPMC_CS_NAND_ADDRESS 0x20
129 #define GPMC_CS_NAND_DATA 0x24
130
131 /* Control Commands */
132 #define GPMC_CONFIG_RDY_BSY 0x00000001
133 #define GPMC_CONFIG_DEV_SIZE 0x00000002
134 #define GPMC_CONFIG_DEV_TYPE 0x00000003
135
136 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
137 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
138 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
139 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
140 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
141 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
142 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
143 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
144 /** CLKACTIVATIONTIME Max Ticks */
145 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
146 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
147 /** ATTACHEDDEVICEPAGELENGTH Max Value */
148 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
149 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
150 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
151 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
152 /** WAITMONITORINGTIME Max Ticks */
153 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
154 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
155 #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
156 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
157 /** DEVICESIZE Max Value */
158 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
159 #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
160 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
161 #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
162 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
163 #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
164 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
165 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
166 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
167 #define GPMC_CONFIG7_CSVALID (1 << 6)
168
169 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
170 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
171 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
172 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
173 /* All CONFIG7 bits except reserved bits */
174 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
175 GPMC_CONFIG7_CSVALID_MASK | \
176 GPMC_CONFIG7_MASKADDRESS_MASK)
177
178 #define GPMC_DEVICETYPE_NOR 0
179 #define GPMC_DEVICETYPE_NAND 2
180 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
181 #define WR_RD_PIN_MONITORING 0x00600000
182
183 /* ECC commands */
184 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
185 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
186 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
187
188 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
189
190 enum gpmc_clk_domain {
191 GPMC_CD_FCLK,
192 GPMC_CD_CLK
193 };
194
195 struct gpmc_cs_data {
196 const char *name;
197
198 #define GPMC_CS_RESERVED (1 << 0)
199 u32 flags;
200
201 struct resource mem;
202 };
203
204 /* Structure to save gpmc cs context */
205 struct gpmc_cs_config {
206 u32 config1;
207 u32 config2;
208 u32 config3;
209 u32 config4;
210 u32 config5;
211 u32 config6;
212 u32 config7;
213 int is_valid;
214 };
215
216 /*
217 * Structure to save/restore gpmc context
218 * to support core off on OMAP3
219 */
220 struct omap3_gpmc_regs {
221 u32 sysconfig;
222 u32 irqenable;
223 u32 timeout_ctrl;
224 u32 config;
225 u32 prefetch_config1;
226 u32 prefetch_config2;
227 u32 prefetch_control;
228 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
229 };
230
231 struct gpmc_device {
232 struct device *dev;
233 int irq;
234 struct irq_chip irq_chip;
235 struct gpio_chip gpio_chip;
236 struct notifier_block nb;
237 struct omap3_gpmc_regs context;
238 int nirqs;
239 unsigned int is_suspended:1;
240 };
241
242 static struct irq_domain *gpmc_irq_domain;
243
244 static struct resource gpmc_mem_root;
245 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
246 static DEFINE_SPINLOCK(gpmc_mem_lock);
247 /* Define chip-selects as reserved by default until probe completes */
248 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
249 static unsigned int gpmc_nr_waitpins;
250 static unsigned int gpmc_capability;
251 static void __iomem *gpmc_base;
252
253 static struct clk *gpmc_l3_clk;
254
255 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
256
gpmc_write_reg(int idx,u32 val)257 static void gpmc_write_reg(int idx, u32 val)
258 {
259 writel_relaxed(val, gpmc_base + idx);
260 }
261
gpmc_read_reg(int idx)262 static u32 gpmc_read_reg(int idx)
263 {
264 return readl_relaxed(gpmc_base + idx);
265 }
266
gpmc_cs_write_reg(int cs,int idx,u32 val)267 void gpmc_cs_write_reg(int cs, int idx, u32 val)
268 {
269 void __iomem *reg_addr;
270
271 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
272 writel_relaxed(val, reg_addr);
273 }
274
gpmc_cs_read_reg(int cs,int idx)275 static u32 gpmc_cs_read_reg(int cs, int idx)
276 {
277 void __iomem *reg_addr;
278
279 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
280 return readl_relaxed(reg_addr);
281 }
282
283 /* TODO: Add support for gpmc_fck to clock framework and use it */
gpmc_get_fclk_period(void)284 static unsigned long gpmc_get_fclk_period(void)
285 {
286 unsigned long rate = clk_get_rate(gpmc_l3_clk);
287
288 rate /= 1000;
289 rate = 1000000000 / rate; /* In picoseconds */
290
291 return rate;
292 }
293
294 /**
295 * gpmc_get_clk_period - get period of selected clock domain in ps
296 * @cs: Chip Select Region.
297 * @cd: Clock Domain.
298 *
299 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
300 * prior to calling this function with GPMC_CD_CLK.
301 */
gpmc_get_clk_period(int cs,enum gpmc_clk_domain cd)302 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
303 {
304 unsigned long tick_ps = gpmc_get_fclk_period();
305 u32 l;
306 int div;
307
308 switch (cd) {
309 case GPMC_CD_CLK:
310 /* get current clk divider */
311 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
312 div = (l & 0x03) + 1;
313 /* get GPMC_CLK period */
314 tick_ps *= div;
315 break;
316 case GPMC_CD_FCLK:
317 default:
318 break;
319 }
320
321 return tick_ps;
322 }
323
gpmc_ns_to_clk_ticks(unsigned int time_ns,int cs,enum gpmc_clk_domain cd)324 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
325 enum gpmc_clk_domain cd)
326 {
327 unsigned long tick_ps;
328
329 /* Calculate in picosecs to yield more exact results */
330 tick_ps = gpmc_get_clk_period(cs, cd);
331
332 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
333 }
334
gpmc_ns_to_ticks(unsigned int time_ns)335 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
336 {
337 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
338 }
339
gpmc_ps_to_ticks(unsigned int time_ps)340 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
341 {
342 unsigned long tick_ps;
343
344 /* Calculate in picosecs to yield more exact results */
345 tick_ps = gpmc_get_fclk_period();
346
347 return (time_ps + tick_ps - 1) / tick_ps;
348 }
349
gpmc_clk_ticks_to_ns(unsigned int ticks,int cs,enum gpmc_clk_domain cd)350 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
351 enum gpmc_clk_domain cd)
352 {
353 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
354 }
355
gpmc_ticks_to_ns(unsigned int ticks)356 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
357 {
358 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
359 }
360
gpmc_ticks_to_ps(unsigned int ticks)361 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
362 {
363 return ticks * gpmc_get_fclk_period();
364 }
365
gpmc_round_ps_to_ticks(unsigned int time_ps)366 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
367 {
368 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
369
370 return ticks * gpmc_get_fclk_period();
371 }
372
gpmc_cs_modify_reg(int cs,int reg,u32 mask,bool value)373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
374 {
375 u32 l;
376
377 l = gpmc_cs_read_reg(cs, reg);
378 if (value)
379 l |= mask;
380 else
381 l &= ~mask;
382 gpmc_cs_write_reg(cs, reg, l);
383 }
384
gpmc_cs_bool_timings(int cs,const struct gpmc_bool_timings * p)385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
386 {
387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
388 GPMC_CONFIG1_TIME_PARA_GRAN,
389 p->time_para_granularity);
390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
391 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
393 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
395 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
397 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
399 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
400 p->cycle2cyclesamecsen);
401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
402 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
403 p->cycle2cyclediffcsen);
404 }
405
406 #ifdef CONFIG_OMAP_GPMC_DEBUG
407 /**
408 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
409 * @cs: Chip Select Region
410 * @reg: GPMC_CS_CONFIGn register offset.
411 * @st_bit: Start Bit
412 * @end_bit: End Bit. Must be >= @st_bit.
413 * @max: Maximum parameter value (before optional @shift).
414 * If 0, maximum is as high as @st_bit and @end_bit allow.
415 * @name: DTS node name, w/o "gpmc,"
416 * @cd: Clock Domain of timing parameter.
417 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
418 * @raw: Raw Format Option.
419 * raw format: gpmc,name = <value>
420 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
421 * Where x ns -- y ns result in the same tick value.
422 * When @max is exceeded, "invalid" is printed inside comment.
423 * @noval: Parameter values equal to 0 are not printed.
424 * @return: Specified timing parameter (after optional @shift).
425 *
426 */
get_gpmc_timing_reg(int cs,int reg,int st_bit,int end_bit,int max,const char * name,const enum gpmc_clk_domain cd,int shift,bool raw,bool noval)427 static int get_gpmc_timing_reg(
428 /* timing specifiers */
429 int cs, int reg, int st_bit, int end_bit, int max,
430 const char *name, const enum gpmc_clk_domain cd,
431 /* value transform */
432 int shift,
433 /* format specifiers */
434 bool raw, bool noval)
435 {
436 u32 l;
437 int nr_bits;
438 int mask;
439 bool invalid;
440
441 l = gpmc_cs_read_reg(cs, reg);
442 nr_bits = end_bit - st_bit + 1;
443 mask = (1 << nr_bits) - 1;
444 l = (l >> st_bit) & mask;
445 if (!max)
446 max = mask;
447 invalid = l > max;
448 if (shift)
449 l = (shift << l);
450 if (noval && (l == 0))
451 return 0;
452 if (!raw) {
453 /* DTS tick format for timings in ns */
454 unsigned int time_ns;
455 unsigned int time_ns_min = 0;
456
457 if (l)
458 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
459 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
460 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
461 name, time_ns, time_ns_min, time_ns, l,
462 invalid ? "; invalid " : " ");
463 } else {
464 /* raw format */
465 pr_info("gpmc,%s = <%u>;%s\n", name, l,
466 invalid ? " /* invalid */" : "");
467 }
468
469 return l;
470 }
471
472 #define GPMC_PRINT_CONFIG(cs, config) \
473 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
474 gpmc_cs_read_reg(cs, config))
475 #define GPMC_GET_RAW(reg, st, end, field) \
476 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
477 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
478 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
479 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
480 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
481 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
482 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
483 #define GPMC_GET_TICKS(reg, st, end, field) \
484 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
485 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
486 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
487 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
488 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
489
gpmc_show_regs(int cs,const char * desc)490 static void gpmc_show_regs(int cs, const char *desc)
491 {
492 pr_info("gpmc cs%i %s:\n", cs, desc);
493 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
494 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
499 }
500
501 /*
502 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
503 * see commit c9fb809.
504 */
gpmc_cs_show_timings(int cs,const char * desc)505 static void gpmc_cs_show_timings(int cs, const char *desc)
506 {
507 gpmc_show_regs(cs, desc);
508
509 pr_info("gpmc cs%i access configuration:\n", cs);
510 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
511 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
512 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
513 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
514 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
515 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
516 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
517 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
518 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
519 "burst-length");
520 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
521 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
525
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
527
528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
529
530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
532
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
535
536 pr_info("gpmc cs%i timings configuration:\n", cs);
537 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
538 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
539 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
540
541 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
542 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
543 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
544 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
547 "adv-aad-mux-rd-off-ns");
548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
549 "adv-aad-mux-wr-off-ns");
550 }
551
552 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
553 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
554 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
557 }
558 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
560
561 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
562 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
563 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
564
565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
566
567 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
568 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
569
570 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
571 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
572 "wait-monitoring-ns", GPMC_CD_CLK);
573 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
574 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
575 "clk-activation-ns", GPMC_CD_FCLK);
576
577 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
578 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
579 }
580 #else
gpmc_cs_show_timings(int cs,const char * desc)581 static inline void gpmc_cs_show_timings(int cs, const char *desc)
582 {
583 }
584 #endif
585
586 /**
587 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
588 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
589 * prior to calling this function with @cd equal to GPMC_CD_CLK.
590 *
591 * @cs: Chip Select Region.
592 * @reg: GPMC_CS_CONFIGn register offset.
593 * @st_bit: Start Bit
594 * @end_bit: End Bit. Must be >= @st_bit.
595 * @max: Maximum parameter value.
596 * If 0, maximum is as high as @st_bit and @end_bit allow.
597 * @time: Timing parameter in ns.
598 * @cd: Timing parameter clock domain.
599 * @name: Timing parameter name.
600 * @return: 0 on success, -1 on error.
601 */
set_gpmc_timing_reg(int cs,int reg,int st_bit,int end_bit,int max,int time,enum gpmc_clk_domain cd,const char * name)602 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
603 int time, enum gpmc_clk_domain cd, const char *name)
604 {
605 u32 l;
606 int ticks, mask, nr_bits;
607
608 if (time == 0)
609 ticks = 0;
610 else
611 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
612 nr_bits = end_bit - st_bit + 1;
613 mask = (1 << nr_bits) - 1;
614
615 if (!max)
616 max = mask;
617
618 if (ticks > max) {
619 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
620 __func__, cs, name, time, ticks, max);
621
622 return -1;
623 }
624
625 l = gpmc_cs_read_reg(cs, reg);
626 #ifdef CONFIG_OMAP_GPMC_DEBUG
627 pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
628 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
629 (l >> st_bit) & mask, time);
630 #endif
631 l &= ~(mask << st_bit);
632 l |= ticks << st_bit;
633 gpmc_cs_write_reg(cs, reg, l);
634
635 return 0;
636 }
637
638 /**
639 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
640 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
641 * read --> don't sample bus too early
642 * write --> data is longer on bus
643 *
644 * Formula:
645 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
646 * / waitmonitoring_ticks)
647 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
648 * div <= 0 check.
649 *
650 * @wait_monitoring: WAITMONITORINGTIME in ns.
651 * @return: -1 on failure to scale, else proper divider > 0.
652 */
gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)653 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
654 {
655 int div = gpmc_ns_to_ticks(wait_monitoring);
656
657 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
658 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
659
660 if (div > 4)
661 return -1;
662 if (div <= 0)
663 div = 1;
664
665 return div;
666 }
667
668 /**
669 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
670 * @sync_clk: GPMC_CLK period in ps.
671 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
672 * Else, returns -1.
673 */
gpmc_calc_divider(unsigned int sync_clk)674 int gpmc_calc_divider(unsigned int sync_clk)
675 {
676 int div = gpmc_ps_to_ticks(sync_clk);
677
678 if (div > 4)
679 return -1;
680 if (div <= 0)
681 div = 1;
682
683 return div;
684 }
685
686 /**
687 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
688 * @cs: Chip Select Region.
689 * @t: GPMC timing parameters.
690 * @s: GPMC timing settings.
691 * @return: 0 on success, -1 on error.
692 */
gpmc_cs_set_timings(int cs,const struct gpmc_timings * t,const struct gpmc_settings * s)693 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
694 const struct gpmc_settings *s)
695 {
696 int div, ret;
697 u32 l;
698
699 div = gpmc_calc_divider(t->sync_clk);
700 if (div < 0)
701 return -EINVAL;
702
703 /*
704 * See if we need to change the divider for waitmonitoringtime.
705 *
706 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
707 * pure asynchronous accesses, i.e. both read and write asynchronous.
708 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
709 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
710 *
711 * This statement must not change div to scale async WAITMONITORINGTIME
712 * to protect mixed synchronous and asynchronous accesses.
713 *
714 * We raise an error later if WAITMONITORINGTIME does not fit.
715 */
716 if (!s->sync_read && !s->sync_write &&
717 (s->wait_on_read || s->wait_on_write)
718 ) {
719 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
720 if (div < 0) {
721 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
722 __func__,
723 t->wait_monitoring
724 );
725 return -ENXIO;
726 }
727 }
728
729 ret = 0;
730 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
731 GPMC_CD_FCLK, "cs_on");
732 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
733 GPMC_CD_FCLK, "cs_rd_off");
734 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
735 GPMC_CD_FCLK, "cs_wr_off");
736 if (ret)
737 return -ENXIO;
738
739 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
740 GPMC_CD_FCLK, "adv_on");
741 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
742 GPMC_CD_FCLK, "adv_rd_off");
743 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
744 GPMC_CD_FCLK, "adv_wr_off");
745 if (ret)
746 return -ENXIO;
747
748 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
749 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
750 t->adv_aad_mux_on, GPMC_CD_FCLK,
751 "adv_aad_mux_on");
752 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
753 t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
754 "adv_aad_mux_rd_off");
755 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
756 t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
757 "adv_aad_mux_wr_off");
758 if (ret)
759 return -ENXIO;
760 }
761
762 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
763 GPMC_CD_FCLK, "oe_on");
764 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
765 GPMC_CD_FCLK, "oe_off");
766 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
767 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
768 t->oe_aad_mux_on, GPMC_CD_FCLK,
769 "oe_aad_mux_on");
770 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
771 t->oe_aad_mux_off, GPMC_CD_FCLK,
772 "oe_aad_mux_off");
773 }
774 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
775 GPMC_CD_FCLK, "we_on");
776 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
777 GPMC_CD_FCLK, "we_off");
778 if (ret)
779 return -ENXIO;
780
781 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
782 GPMC_CD_FCLK, "rd_cycle");
783 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
784 GPMC_CD_FCLK, "wr_cycle");
785 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
786 GPMC_CD_FCLK, "access");
787 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
788 t->page_burst_access, GPMC_CD_FCLK,
789 "page_burst_access");
790 if (ret)
791 return -ENXIO;
792
793 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
794 t->bus_turnaround, GPMC_CD_FCLK,
795 "bus_turnaround");
796 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
797 t->cycle2cycle_delay, GPMC_CD_FCLK,
798 "cycle2cycle_delay");
799 if (ret)
800 return -ENXIO;
801
802 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
803 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
804 t->wr_data_mux_bus, GPMC_CD_FCLK,
805 "wr_data_mux_bus");
806 if (ret)
807 return -ENXIO;
808 }
809 if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
810 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
811 t->wr_access, GPMC_CD_FCLK,
812 "wr_access");
813 if (ret)
814 return -ENXIO;
815 }
816
817 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
818 l &= ~0x03;
819 l |= (div - 1);
820 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
821
822 ret = 0;
823 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
824 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
825 t->wait_monitoring, GPMC_CD_CLK,
826 "wait_monitoring");
827 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
828 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
829 t->clk_activation, GPMC_CD_FCLK,
830 "clk_activation");
831 if (ret)
832 return -ENXIO;
833
834 #ifdef CONFIG_OMAP_GPMC_DEBUG
835 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
836 cs, (div * gpmc_get_fclk_period()) / 1000, div);
837 #endif
838
839 gpmc_cs_bool_timings(cs, &t->bool_timings);
840 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
841
842 return 0;
843 }
844
gpmc_cs_set_memconf(int cs,u32 base,u32 size)845 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
846 {
847 u32 l;
848 u32 mask;
849
850 /*
851 * Ensure that base address is aligned on a
852 * boundary equal to or greater than size.
853 */
854 if (base & (size - 1))
855 return -EINVAL;
856
857 base >>= GPMC_CHUNK_SHIFT;
858 mask = (1 << GPMC_SECTION_SHIFT) - size;
859 mask >>= GPMC_CHUNK_SHIFT;
860 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
861
862 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
863 l &= ~GPMC_CONFIG7_MASK;
864 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
865 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
866 l |= GPMC_CONFIG7_CSVALID;
867 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
868
869 return 0;
870 }
871
gpmc_cs_enable_mem(int cs)872 static void gpmc_cs_enable_mem(int cs)
873 {
874 u32 l;
875
876 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
877 l |= GPMC_CONFIG7_CSVALID;
878 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
879 }
880
gpmc_cs_disable_mem(int cs)881 static void gpmc_cs_disable_mem(int cs)
882 {
883 u32 l;
884
885 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
886 l &= ~GPMC_CONFIG7_CSVALID;
887 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
888 }
889
gpmc_cs_get_memconf(int cs,u32 * base,u32 * size)890 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
891 {
892 u32 l;
893 u32 mask;
894
895 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
896 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
897 mask = (l >> 8) & 0x0f;
898 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
899 }
900
gpmc_cs_mem_enabled(int cs)901 static int gpmc_cs_mem_enabled(int cs)
902 {
903 u32 l;
904
905 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
906 return l & GPMC_CONFIG7_CSVALID;
907 }
908
gpmc_cs_set_reserved(int cs,int reserved)909 static void gpmc_cs_set_reserved(int cs, int reserved)
910 {
911 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
912
913 gpmc->flags |= GPMC_CS_RESERVED;
914 }
915
gpmc_cs_reserved(int cs)916 static bool gpmc_cs_reserved(int cs)
917 {
918 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
919
920 return gpmc->flags & GPMC_CS_RESERVED;
921 }
922
gpmc_mem_align(unsigned long size)923 static unsigned long gpmc_mem_align(unsigned long size)
924 {
925 int order;
926
927 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
928 order = GPMC_CHUNK_SHIFT - 1;
929 do {
930 size >>= 1;
931 order++;
932 } while (size);
933 size = 1 << order;
934 return size;
935 }
936
gpmc_cs_insert_mem(int cs,unsigned long base,unsigned long size)937 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
938 {
939 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
940 struct resource *res = &gpmc->mem;
941 int r;
942
943 size = gpmc_mem_align(size);
944 spin_lock(&gpmc_mem_lock);
945 res->start = base;
946 res->end = base + size - 1;
947 r = request_resource(&gpmc_mem_root, res);
948 spin_unlock(&gpmc_mem_lock);
949
950 return r;
951 }
952
gpmc_cs_delete_mem(int cs)953 static int gpmc_cs_delete_mem(int cs)
954 {
955 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
956 struct resource *res = &gpmc->mem;
957 int r;
958
959 spin_lock(&gpmc_mem_lock);
960 r = release_resource(res);
961 res->start = 0;
962 res->end = 0;
963 spin_unlock(&gpmc_mem_lock);
964
965 return r;
966 }
967
gpmc_cs_request(int cs,unsigned long size,unsigned long * base)968 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
969 {
970 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
971 struct resource *res = &gpmc->mem;
972 int r = -1;
973
974 if (cs >= gpmc_cs_num) {
975 pr_err("%s: requested chip-select is disabled\n", __func__);
976 return -ENODEV;
977 }
978 size = gpmc_mem_align(size);
979 if (size > (1 << GPMC_SECTION_SHIFT))
980 return -ENOMEM;
981
982 spin_lock(&gpmc_mem_lock);
983 if (gpmc_cs_reserved(cs)) {
984 r = -EBUSY;
985 goto out;
986 }
987 if (gpmc_cs_mem_enabled(cs))
988 r = adjust_resource(res, res->start & ~(size - 1), size);
989 if (r < 0)
990 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
991 size, NULL, NULL);
992 if (r < 0)
993 goto out;
994
995 /* Disable CS while changing base address and size mask */
996 gpmc_cs_disable_mem(cs);
997
998 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
999 if (r < 0) {
1000 release_resource(res);
1001 goto out;
1002 }
1003
1004 /* Enable CS */
1005 gpmc_cs_enable_mem(cs);
1006 *base = res->start;
1007 gpmc_cs_set_reserved(cs, 1);
1008 out:
1009 spin_unlock(&gpmc_mem_lock);
1010 return r;
1011 }
1012 EXPORT_SYMBOL(gpmc_cs_request);
1013
gpmc_cs_free(int cs)1014 void gpmc_cs_free(int cs)
1015 {
1016 struct gpmc_cs_data *gpmc;
1017 struct resource *res;
1018
1019 spin_lock(&gpmc_mem_lock);
1020 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1021 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
1022 spin_unlock(&gpmc_mem_lock);
1023 return;
1024 }
1025 gpmc = &gpmc_cs[cs];
1026 res = &gpmc->mem;
1027
1028 gpmc_cs_disable_mem(cs);
1029 if (res->flags)
1030 release_resource(res);
1031 gpmc_cs_set_reserved(cs, 0);
1032 spin_unlock(&gpmc_mem_lock);
1033 }
1034 EXPORT_SYMBOL(gpmc_cs_free);
1035
1036 /**
1037 * gpmc_configure - write request to configure gpmc
1038 * @cmd: command type
1039 * @wval: value to write
1040 * @return status of the operation
1041 */
gpmc_configure(int cmd,int wval)1042 int gpmc_configure(int cmd, int wval)
1043 {
1044 u32 regval;
1045
1046 switch (cmd) {
1047 case GPMC_CONFIG_WP:
1048 regval = gpmc_read_reg(GPMC_CONFIG);
1049 if (wval)
1050 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1051 else
1052 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1053 gpmc_write_reg(GPMC_CONFIG, regval);
1054 break;
1055
1056 default:
1057 pr_err("%s: command not supported\n", __func__);
1058 return -EINVAL;
1059 }
1060
1061 return 0;
1062 }
1063 EXPORT_SYMBOL(gpmc_configure);
1064
gpmc_nand_writebuffer_empty(void)1065 static bool gpmc_nand_writebuffer_empty(void)
1066 {
1067 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1068 return true;
1069
1070 return false;
1071 }
1072
1073 static struct gpmc_nand_ops nand_ops = {
1074 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1075 };
1076
1077 /**
1078 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1079 * @reg: the GPMC NAND register map exclusive for NAND use.
1080 * @cs: GPMC chip select number on which the NAND sits. The
1081 * register map returned will be specific to this chip select.
1082 *
1083 * Returns NULL on error e.g. invalid cs.
1084 */
gpmc_omap_get_nand_ops(struct gpmc_nand_regs * reg,int cs)1085 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1086 {
1087 int i;
1088
1089 if (cs >= gpmc_cs_num)
1090 return NULL;
1091
1092 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1093 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1094 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1095 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1096 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1097 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1098 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1099 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1100 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1101 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1102 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1103 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1104 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1105 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1106
1107 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1108 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1109 GPMC_BCH_SIZE * i;
1110 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1111 GPMC_BCH_SIZE * i;
1112 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1113 GPMC_BCH_SIZE * i;
1114 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1115 GPMC_BCH_SIZE * i;
1116 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1117 i * GPMC_BCH_SIZE;
1118 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1119 i * GPMC_BCH_SIZE;
1120 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1121 i * GPMC_BCH_SIZE;
1122 }
1123
1124 return &nand_ops;
1125 }
1126 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1127
gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings * t,struct gpmc_settings * s,int freq,int latency)1128 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1129 struct gpmc_settings *s,
1130 int freq, int latency)
1131 {
1132 struct gpmc_device_timings dev_t;
1133 const int t_cer = 15;
1134 const int t_avdp = 12;
1135 const int t_cez = 20; /* max of t_cez, t_oez */
1136 const int t_wpl = 40;
1137 const int t_wph = 30;
1138 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1139
1140 switch (freq) {
1141 case 104:
1142 min_gpmc_clk_period = 9600; /* 104 MHz */
1143 t_ces = 3;
1144 t_avds = 4;
1145 t_avdh = 2;
1146 t_ach = 3;
1147 t_aavdh = 6;
1148 t_rdyo = 6;
1149 break;
1150 case 83:
1151 min_gpmc_clk_period = 12000; /* 83 MHz */
1152 t_ces = 5;
1153 t_avds = 4;
1154 t_avdh = 2;
1155 t_ach = 6;
1156 t_aavdh = 6;
1157 t_rdyo = 9;
1158 break;
1159 case 66:
1160 min_gpmc_clk_period = 15000; /* 66 MHz */
1161 t_ces = 6;
1162 t_avds = 5;
1163 t_avdh = 2;
1164 t_ach = 6;
1165 t_aavdh = 6;
1166 t_rdyo = 11;
1167 break;
1168 default:
1169 min_gpmc_clk_period = 18500; /* 54 MHz */
1170 t_ces = 7;
1171 t_avds = 7;
1172 t_avdh = 7;
1173 t_ach = 9;
1174 t_aavdh = 7;
1175 t_rdyo = 15;
1176 break;
1177 }
1178
1179 /* Set synchronous read timings */
1180 memset(&dev_t, 0, sizeof(dev_t));
1181
1182 if (!s->sync_write) {
1183 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1184 dev_t.t_wpl = t_wpl * 1000;
1185 dev_t.t_wph = t_wph * 1000;
1186 dev_t.t_aavdh = t_aavdh * 1000;
1187 }
1188 dev_t.ce_xdelay = true;
1189 dev_t.avd_xdelay = true;
1190 dev_t.oe_xdelay = true;
1191 dev_t.we_xdelay = true;
1192 dev_t.clk = min_gpmc_clk_period;
1193 dev_t.t_bacc = dev_t.clk;
1194 dev_t.t_ces = t_ces * 1000;
1195 dev_t.t_avds = t_avds * 1000;
1196 dev_t.t_avdh = t_avdh * 1000;
1197 dev_t.t_ach = t_ach * 1000;
1198 dev_t.cyc_iaa = (latency + 1);
1199 dev_t.t_cez_r = t_cez * 1000;
1200 dev_t.t_cez_w = dev_t.t_cez_r;
1201 dev_t.cyc_aavdh_oe = 1;
1202 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1203
1204 gpmc_calc_timings(t, s, &dev_t);
1205 }
1206
gpmc_omap_onenand_set_timings(struct device * dev,int cs,int freq,int latency,struct gpmc_onenand_info * info)1207 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1208 int latency,
1209 struct gpmc_onenand_info *info)
1210 {
1211 int ret;
1212 struct gpmc_timings gpmc_t;
1213 struct gpmc_settings gpmc_s;
1214
1215 gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1216
1217 info->sync_read = gpmc_s.sync_read;
1218 info->sync_write = gpmc_s.sync_write;
1219 info->burst_len = gpmc_s.burst_len;
1220
1221 if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1222 return 0;
1223
1224 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1225
1226 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1227 if (ret < 0)
1228 return ret;
1229
1230 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1231 }
1232 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1233
gpmc_get_client_irq(unsigned int irq_config)1234 int gpmc_get_client_irq(unsigned int irq_config)
1235 {
1236 if (!gpmc_irq_domain) {
1237 pr_warn("%s called before GPMC IRQ domain available\n",
1238 __func__);
1239 return 0;
1240 }
1241
1242 /* we restrict this to NAND IRQs only */
1243 if (irq_config >= GPMC_NR_NAND_IRQS)
1244 return 0;
1245
1246 return irq_create_mapping(gpmc_irq_domain, irq_config);
1247 }
1248
gpmc_irq_endis(unsigned long hwirq,bool endis)1249 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1250 {
1251 u32 regval;
1252
1253 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1254 if (hwirq >= GPMC_NR_NAND_IRQS)
1255 hwirq += 8 - GPMC_NR_NAND_IRQS;
1256
1257 regval = gpmc_read_reg(GPMC_IRQENABLE);
1258 if (endis)
1259 regval |= BIT(hwirq);
1260 else
1261 regval &= ~BIT(hwirq);
1262 gpmc_write_reg(GPMC_IRQENABLE, regval);
1263
1264 return 0;
1265 }
1266
gpmc_irq_disable(struct irq_data * p)1267 static void gpmc_irq_disable(struct irq_data *p)
1268 {
1269 gpmc_irq_endis(p->hwirq, false);
1270 }
1271
gpmc_irq_enable(struct irq_data * p)1272 static void gpmc_irq_enable(struct irq_data *p)
1273 {
1274 gpmc_irq_endis(p->hwirq, true);
1275 }
1276
gpmc_irq_mask(struct irq_data * d)1277 static void gpmc_irq_mask(struct irq_data *d)
1278 {
1279 gpmc_irq_endis(d->hwirq, false);
1280 }
1281
gpmc_irq_unmask(struct irq_data * d)1282 static void gpmc_irq_unmask(struct irq_data *d)
1283 {
1284 gpmc_irq_endis(d->hwirq, true);
1285 }
1286
gpmc_irq_edge_config(unsigned long hwirq,bool rising_edge)1287 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1288 {
1289 u32 regval;
1290
1291 /* NAND IRQs polarity is not configurable */
1292 if (hwirq < GPMC_NR_NAND_IRQS)
1293 return;
1294
1295 /* WAITPIN starts at BIT 8 */
1296 hwirq += 8 - GPMC_NR_NAND_IRQS;
1297
1298 regval = gpmc_read_reg(GPMC_CONFIG);
1299 if (rising_edge)
1300 regval &= ~BIT(hwirq);
1301 else
1302 regval |= BIT(hwirq);
1303
1304 gpmc_write_reg(GPMC_CONFIG, regval);
1305 }
1306
gpmc_irq_ack(struct irq_data * d)1307 static void gpmc_irq_ack(struct irq_data *d)
1308 {
1309 unsigned int hwirq = d->hwirq;
1310
1311 /* skip reserved bits */
1312 if (hwirq >= GPMC_NR_NAND_IRQS)
1313 hwirq += 8 - GPMC_NR_NAND_IRQS;
1314
1315 /* Setting bit to 1 clears (or Acks) the interrupt */
1316 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1317 }
1318
gpmc_irq_set_type(struct irq_data * d,unsigned int trigger)1319 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1320 {
1321 /* can't set type for NAND IRQs */
1322 if (d->hwirq < GPMC_NR_NAND_IRQS)
1323 return -EINVAL;
1324
1325 /* We can support either rising or falling edge at a time */
1326 if (trigger == IRQ_TYPE_EDGE_FALLING)
1327 gpmc_irq_edge_config(d->hwirq, false);
1328 else if (trigger == IRQ_TYPE_EDGE_RISING)
1329 gpmc_irq_edge_config(d->hwirq, true);
1330 else
1331 return -EINVAL;
1332
1333 return 0;
1334 }
1335
gpmc_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hw)1336 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1337 irq_hw_number_t hw)
1338 {
1339 struct gpmc_device *gpmc = d->host_data;
1340
1341 irq_set_chip_data(virq, gpmc);
1342 if (hw < GPMC_NR_NAND_IRQS) {
1343 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1344 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1345 handle_simple_irq);
1346 } else {
1347 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1348 handle_edge_irq);
1349 }
1350
1351 return 0;
1352 }
1353
1354 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1355 .map = gpmc_irq_map,
1356 .xlate = irq_domain_xlate_twocell,
1357 };
1358
gpmc_handle_irq(int irq,void * data)1359 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1360 {
1361 int hwirq, virq;
1362 u32 regval, regvalx;
1363 struct gpmc_device *gpmc = data;
1364
1365 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1366 regvalx = regval;
1367
1368 if (!regval)
1369 return IRQ_NONE;
1370
1371 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1372 /* skip reserved status bits */
1373 if (hwirq == GPMC_NR_NAND_IRQS)
1374 regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1375
1376 if (regvalx & BIT(hwirq)) {
1377 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1378 if (!virq) {
1379 dev_warn(gpmc->dev,
1380 "spurious irq detected hwirq %d, virq %d\n",
1381 hwirq, virq);
1382 }
1383
1384 generic_handle_irq(virq);
1385 }
1386 }
1387
1388 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1389
1390 return IRQ_HANDLED;
1391 }
1392
gpmc_setup_irq(struct gpmc_device * gpmc)1393 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1394 {
1395 u32 regval;
1396 int rc;
1397
1398 /* Disable interrupts */
1399 gpmc_write_reg(GPMC_IRQENABLE, 0);
1400
1401 /* clear interrupts */
1402 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1403 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1404
1405 gpmc->irq_chip.name = "gpmc";
1406 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1407 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1408 gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1409 gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1410 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1411 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1412
1413 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1414 gpmc->nirqs,
1415 &gpmc_irq_domain_ops,
1416 gpmc);
1417 if (!gpmc_irq_domain) {
1418 dev_err(gpmc->dev, "IRQ domain add failed\n");
1419 return -ENODEV;
1420 }
1421
1422 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1423 if (rc) {
1424 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1425 gpmc->irq, rc);
1426 irq_domain_remove(gpmc_irq_domain);
1427 gpmc_irq_domain = NULL;
1428 }
1429
1430 return rc;
1431 }
1432
gpmc_free_irq(struct gpmc_device * gpmc)1433 static int gpmc_free_irq(struct gpmc_device *gpmc)
1434 {
1435 int hwirq;
1436
1437 free_irq(gpmc->irq, gpmc);
1438
1439 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1440 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1441
1442 irq_domain_remove(gpmc_irq_domain);
1443 gpmc_irq_domain = NULL;
1444
1445 return 0;
1446 }
1447
gpmc_mem_exit(void)1448 static void gpmc_mem_exit(void)
1449 {
1450 int cs;
1451
1452 for (cs = 0; cs < gpmc_cs_num; cs++) {
1453 if (!gpmc_cs_mem_enabled(cs))
1454 continue;
1455 gpmc_cs_delete_mem(cs);
1456 }
1457 }
1458
gpmc_mem_init(void)1459 static void gpmc_mem_init(void)
1460 {
1461 int cs;
1462
1463 gpmc_mem_root.start = GPMC_MEM_START;
1464 gpmc_mem_root.end = GPMC_MEM_END;
1465
1466 /* Reserve all regions that has been set up by bootloader */
1467 for (cs = 0; cs < gpmc_cs_num; cs++) {
1468 u32 base, size;
1469
1470 if (!gpmc_cs_mem_enabled(cs))
1471 continue;
1472 gpmc_cs_get_memconf(cs, &base, &size);
1473 if (gpmc_cs_insert_mem(cs, base, size)) {
1474 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1475 __func__, cs, base, base + size);
1476 gpmc_cs_disable_mem(cs);
1477 }
1478 }
1479 }
1480
gpmc_round_ps_to_sync_clk(u32 time_ps,u32 sync_clk)1481 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1482 {
1483 u32 temp;
1484 int div;
1485
1486 div = gpmc_calc_divider(sync_clk);
1487 temp = gpmc_ps_to_ticks(time_ps);
1488 temp = (temp + div - 1) / div;
1489 return gpmc_ticks_to_ps(temp * div);
1490 }
1491
1492 /* XXX: can the cycles be avoided ? */
gpmc_calc_sync_read_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1493 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1494 struct gpmc_device_timings *dev_t,
1495 bool mux)
1496 {
1497 u32 temp;
1498
1499 /* adv_rd_off */
1500 temp = dev_t->t_avdp_r;
1501 /* XXX: mux check required ? */
1502 if (mux) {
1503 /* XXX: t_avdp not to be required for sync, only added for tusb
1504 * this indirectly necessitates requirement of t_avdp_r and
1505 * t_avdp_w instead of having a single t_avdp
1506 */
1507 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1508 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1509 }
1510 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1511
1512 /* oe_on */
1513 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1514 if (mux) {
1515 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1516 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1517 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1518 }
1519 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1520
1521 /* access */
1522 /* XXX: any scope for improvement ?, by combining oe_on
1523 * and clk_activation, need to check whether
1524 * access = clk_activation + round to sync clk ?
1525 */
1526 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1527 temp += gpmc_t->clk_activation;
1528 if (dev_t->cyc_oe)
1529 temp = max_t(u32, temp, gpmc_t->oe_on +
1530 gpmc_ticks_to_ps(dev_t->cyc_oe));
1531 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1532
1533 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1534 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1535
1536 /* rd_cycle */
1537 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1538 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1539 gpmc_t->access;
1540 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1541 if (dev_t->t_ce_rdyz)
1542 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1543 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1544
1545 return 0;
1546 }
1547
gpmc_calc_sync_write_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1548 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1549 struct gpmc_device_timings *dev_t,
1550 bool mux)
1551 {
1552 u32 temp;
1553
1554 /* adv_wr_off */
1555 temp = dev_t->t_avdp_w;
1556 if (mux) {
1557 temp = max_t(u32, temp,
1558 gpmc_t->clk_activation + dev_t->t_avdh);
1559 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1560 }
1561 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1562
1563 /* wr_data_mux_bus */
1564 temp = max_t(u32, dev_t->t_weasu,
1565 gpmc_t->clk_activation + dev_t->t_rdyo);
1566 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1567 * and in that case remember to handle we_on properly
1568 */
1569 if (mux) {
1570 temp = max_t(u32, temp,
1571 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1572 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1573 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1574 }
1575 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1576
1577 /* we_on */
1578 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1579 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1580 else
1581 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1582
1583 /* wr_access */
1584 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1585 gpmc_t->wr_access = gpmc_t->access;
1586
1587 /* we_off */
1588 temp = gpmc_t->we_on + dev_t->t_wpl;
1589 temp = max_t(u32, temp,
1590 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1591 temp = max_t(u32, temp,
1592 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1593 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1594
1595 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1596 dev_t->t_wph);
1597
1598 /* wr_cycle */
1599 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1600 temp += gpmc_t->wr_access;
1601 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1602 if (dev_t->t_ce_rdyz)
1603 temp = max_t(u32, temp,
1604 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1605 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1606
1607 return 0;
1608 }
1609
gpmc_calc_async_read_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1610 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1611 struct gpmc_device_timings *dev_t,
1612 bool mux)
1613 {
1614 u32 temp;
1615
1616 /* adv_rd_off */
1617 temp = dev_t->t_avdp_r;
1618 if (mux)
1619 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1620 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1621
1622 /* oe_on */
1623 temp = dev_t->t_oeasu;
1624 if (mux)
1625 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
1626 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1627
1628 /* access */
1629 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1630 gpmc_t->oe_on + dev_t->t_oe);
1631 temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1632 temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
1633 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1634
1635 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1636 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1637
1638 /* rd_cycle */
1639 temp = max_t(u32, dev_t->t_rd_cycle,
1640 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1641 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1642 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1643
1644 return 0;
1645 }
1646
gpmc_calc_async_write_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1647 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1648 struct gpmc_device_timings *dev_t,
1649 bool mux)
1650 {
1651 u32 temp;
1652
1653 /* adv_wr_off */
1654 temp = dev_t->t_avdp_w;
1655 if (mux)
1656 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1657 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1658
1659 /* wr_data_mux_bus */
1660 temp = dev_t->t_weasu;
1661 if (mux) {
1662 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1663 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1664 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1665 }
1666 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1667
1668 /* we_on */
1669 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1670 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1671 else
1672 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1673
1674 /* we_off */
1675 temp = gpmc_t->we_on + dev_t->t_wpl;
1676 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1677
1678 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1679 dev_t->t_wph);
1680
1681 /* wr_cycle */
1682 temp = max_t(u32, dev_t->t_wr_cycle,
1683 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1684 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1685
1686 return 0;
1687 }
1688
gpmc_calc_sync_common_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t)1689 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1690 struct gpmc_device_timings *dev_t)
1691 {
1692 u32 temp;
1693
1694 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1695 gpmc_get_fclk_period();
1696
1697 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1698 dev_t->t_bacc,
1699 gpmc_t->sync_clk);
1700
1701 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1702 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1703
1704 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1705 return 0;
1706
1707 if (dev_t->ce_xdelay)
1708 gpmc_t->bool_timings.cs_extra_delay = true;
1709 if (dev_t->avd_xdelay)
1710 gpmc_t->bool_timings.adv_extra_delay = true;
1711 if (dev_t->oe_xdelay)
1712 gpmc_t->bool_timings.oe_extra_delay = true;
1713 if (dev_t->we_xdelay)
1714 gpmc_t->bool_timings.we_extra_delay = true;
1715
1716 return 0;
1717 }
1718
gpmc_calc_common_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool sync)1719 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1720 struct gpmc_device_timings *dev_t,
1721 bool sync)
1722 {
1723 u32 temp;
1724
1725 /* cs_on */
1726 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1727
1728 /* adv_on */
1729 temp = dev_t->t_avdasu;
1730 if (dev_t->t_ce_avd)
1731 temp = max_t(u32, temp,
1732 gpmc_t->cs_on + dev_t->t_ce_avd);
1733 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1734
1735 if (sync)
1736 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1737
1738 return 0;
1739 }
1740
1741 /*
1742 * TODO: remove this function once all peripherals are confirmed to
1743 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1744 * has to be modified to handle timings in ps instead of ns
1745 */
gpmc_convert_ps_to_ns(struct gpmc_timings * t)1746 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1747 {
1748 t->cs_on /= 1000;
1749 t->cs_rd_off /= 1000;
1750 t->cs_wr_off /= 1000;
1751 t->adv_on /= 1000;
1752 t->adv_rd_off /= 1000;
1753 t->adv_wr_off /= 1000;
1754 t->we_on /= 1000;
1755 t->we_off /= 1000;
1756 t->oe_on /= 1000;
1757 t->oe_off /= 1000;
1758 t->page_burst_access /= 1000;
1759 t->access /= 1000;
1760 t->rd_cycle /= 1000;
1761 t->wr_cycle /= 1000;
1762 t->bus_turnaround /= 1000;
1763 t->cycle2cycle_delay /= 1000;
1764 t->wait_monitoring /= 1000;
1765 t->clk_activation /= 1000;
1766 t->wr_access /= 1000;
1767 t->wr_data_mux_bus /= 1000;
1768 }
1769
gpmc_calc_timings(struct gpmc_timings * gpmc_t,struct gpmc_settings * gpmc_s,struct gpmc_device_timings * dev_t)1770 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1771 struct gpmc_settings *gpmc_s,
1772 struct gpmc_device_timings *dev_t)
1773 {
1774 bool mux = false, sync = false;
1775
1776 if (gpmc_s) {
1777 mux = gpmc_s->mux_add_data ? true : false;
1778 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1779 }
1780
1781 memset(gpmc_t, 0, sizeof(*gpmc_t));
1782
1783 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1784
1785 if (gpmc_s && gpmc_s->sync_read)
1786 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1787 else
1788 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1789
1790 if (gpmc_s && gpmc_s->sync_write)
1791 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1792 else
1793 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1794
1795 /* TODO: remove, see function definition */
1796 gpmc_convert_ps_to_ns(gpmc_t);
1797
1798 return 0;
1799 }
1800
1801 /**
1802 * gpmc_cs_program_settings - programs non-timing related settings
1803 * @cs: GPMC chip-select to program
1804 * @p: pointer to GPMC settings structure
1805 *
1806 * Programs non-timing related settings for a GPMC chip-select, such as
1807 * bus-width, burst configuration, etc. Function should be called once
1808 * for each chip-select that is being used and must be called before
1809 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1810 * register will be initialised to zero by this function. Returns 0 on
1811 * success and appropriate negative error code on failure.
1812 */
gpmc_cs_program_settings(int cs,struct gpmc_settings * p)1813 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1814 {
1815 u32 config1;
1816
1817 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1818 pr_err("%s: invalid width %d!", __func__, p->device_width);
1819 return -EINVAL;
1820 }
1821
1822 /* Address-data multiplexing not supported for NAND devices */
1823 if (p->device_nand && p->mux_add_data) {
1824 pr_err("%s: invalid configuration!\n", __func__);
1825 return -EINVAL;
1826 }
1827
1828 if ((p->mux_add_data > GPMC_MUX_AD) ||
1829 ((p->mux_add_data == GPMC_MUX_AAD) &&
1830 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1831 pr_err("%s: invalid multiplex configuration!\n", __func__);
1832 return -EINVAL;
1833 }
1834
1835 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1836 if (p->burst_read || p->burst_write) {
1837 switch (p->burst_len) {
1838 case GPMC_BURST_4:
1839 case GPMC_BURST_8:
1840 case GPMC_BURST_16:
1841 break;
1842 default:
1843 pr_err("%s: invalid page/burst-length (%d)\n",
1844 __func__, p->burst_len);
1845 return -EINVAL;
1846 }
1847 }
1848
1849 if (p->wait_pin > gpmc_nr_waitpins) {
1850 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1851 return -EINVAL;
1852 }
1853
1854 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1855
1856 if (p->sync_read)
1857 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1858 if (p->sync_write)
1859 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1860 if (p->wait_on_read)
1861 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1862 if (p->wait_on_write)
1863 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1864 if (p->wait_on_read || p->wait_on_write)
1865 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1866 if (p->device_nand)
1867 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1868 if (p->mux_add_data)
1869 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1870 if (p->burst_read)
1871 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1872 if (p->burst_write)
1873 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1874 if (p->burst_read || p->burst_write) {
1875 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1876 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1877 }
1878
1879 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1880
1881 return 0;
1882 }
1883
1884 #ifdef CONFIG_OF
1885 static const struct of_device_id gpmc_dt_ids[] = {
1886 { .compatible = "ti,omap2420-gpmc" },
1887 { .compatible = "ti,omap2430-gpmc" },
1888 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1889 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1890 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1891 { }
1892 };
1893
gpmc_cs_set_name(int cs,const char * name)1894 static void gpmc_cs_set_name(int cs, const char *name)
1895 {
1896 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1897
1898 gpmc->name = name;
1899 }
1900
gpmc_cs_get_name(int cs)1901 static const char *gpmc_cs_get_name(int cs)
1902 {
1903 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1904
1905 return gpmc->name;
1906 }
1907
1908 /**
1909 * gpmc_cs_remap - remaps a chip-select physical base address
1910 * @cs: chip-select to remap
1911 * @base: physical base address to re-map chip-select to
1912 *
1913 * Re-maps a chip-select to a new physical base address specified by
1914 * "base". Returns 0 on success and appropriate negative error code
1915 * on failure.
1916 */
gpmc_cs_remap(int cs,u32 base)1917 static int gpmc_cs_remap(int cs, u32 base)
1918 {
1919 int ret;
1920 u32 old_base, size;
1921
1922 if (cs >= gpmc_cs_num) {
1923 pr_err("%s: requested chip-select is disabled\n", __func__);
1924 return -ENODEV;
1925 }
1926
1927 /*
1928 * Make sure we ignore any device offsets from the GPMC partition
1929 * allocated for the chip select and that the new base confirms
1930 * to the GPMC 16MB minimum granularity.
1931 */
1932 base &= ~(SZ_16M - 1);
1933
1934 gpmc_cs_get_memconf(cs, &old_base, &size);
1935 if (base == old_base)
1936 return 0;
1937
1938 ret = gpmc_cs_delete_mem(cs);
1939 if (ret < 0)
1940 return ret;
1941
1942 ret = gpmc_cs_insert_mem(cs, base, size);
1943 if (ret < 0)
1944 return ret;
1945
1946 ret = gpmc_cs_set_memconf(cs, base, size);
1947
1948 return ret;
1949 }
1950
1951 /**
1952 * gpmc_read_settings_dt - read gpmc settings from device-tree
1953 * @np: pointer to device-tree node for a gpmc child device
1954 * @p: pointer to gpmc settings structure
1955 *
1956 * Reads the GPMC settings for a GPMC child device from device-tree and
1957 * stores them in the GPMC settings structure passed. The GPMC settings
1958 * structure is initialised to zero by this function and so any
1959 * previously stored settings will be cleared.
1960 */
gpmc_read_settings_dt(struct device_node * np,struct gpmc_settings * p)1961 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1962 {
1963 memset(p, 0, sizeof(struct gpmc_settings));
1964
1965 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1966 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1967 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1968 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1969
1970 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1971 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1972 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1973 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1974 if (!p->burst_read && !p->burst_write)
1975 pr_warn("%s: page/burst-length set but not used!\n",
1976 __func__);
1977 }
1978
1979 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1980 p->wait_on_read = of_property_read_bool(np,
1981 "gpmc,wait-on-read");
1982 p->wait_on_write = of_property_read_bool(np,
1983 "gpmc,wait-on-write");
1984 if (!p->wait_on_read && !p->wait_on_write)
1985 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1986 __func__);
1987 }
1988 }
1989
gpmc_read_timings_dt(struct device_node * np,struct gpmc_timings * gpmc_t)1990 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1991 struct gpmc_timings *gpmc_t)
1992 {
1993 struct gpmc_bool_timings *p;
1994
1995 if (!np || !gpmc_t)
1996 return;
1997
1998 memset(gpmc_t, 0, sizeof(*gpmc_t));
1999
2000 /* minimum clock period for syncronous mode */
2001 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
2002
2003 /* chip select timtings */
2004 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
2005 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
2006 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
2007
2008 /* ADV signal timings */
2009 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
2010 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
2011 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2012 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
2013 &gpmc_t->adv_aad_mux_on);
2014 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
2015 &gpmc_t->adv_aad_mux_rd_off);
2016 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
2017 &gpmc_t->adv_aad_mux_wr_off);
2018
2019 /* WE signal timings */
2020 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
2021 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
2022
2023 /* OE signal timings */
2024 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
2025 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2026 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
2027 &gpmc_t->oe_aad_mux_on);
2028 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
2029 &gpmc_t->oe_aad_mux_off);
2030
2031 /* access and cycle timings */
2032 of_property_read_u32(np, "gpmc,page-burst-access-ns",
2033 &gpmc_t->page_burst_access);
2034 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
2035 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
2036 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
2037 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
2038 &gpmc_t->bus_turnaround);
2039 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2040 &gpmc_t->cycle2cycle_delay);
2041 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2042 &gpmc_t->wait_monitoring);
2043 of_property_read_u32(np, "gpmc,clk-activation-ns",
2044 &gpmc_t->clk_activation);
2045
2046 /* only applicable to OMAP3+ */
2047 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2048 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2049 &gpmc_t->wr_data_mux_bus);
2050
2051 /* bool timing parameters */
2052 p = &gpmc_t->bool_timings;
2053
2054 p->cycle2cyclediffcsen =
2055 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2056 p->cycle2cyclesamecsen =
2057 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2058 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2059 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2060 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2061 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2062 p->time_para_granularity =
2063 of_property_read_bool(np, "gpmc,time-para-granularity");
2064 }
2065
2066 /**
2067 * gpmc_probe_generic_child - configures the gpmc for a child device
2068 * @pdev: pointer to gpmc platform device
2069 * @child: pointer to device-tree node for child device
2070 *
2071 * Allocates and configures a GPMC chip-select for a child device.
2072 * Returns 0 on success and appropriate negative error code on failure.
2073 */
gpmc_probe_generic_child(struct platform_device * pdev,struct device_node * child)2074 static int gpmc_probe_generic_child(struct platform_device *pdev,
2075 struct device_node *child)
2076 {
2077 struct gpmc_settings gpmc_s;
2078 struct gpmc_timings gpmc_t;
2079 struct resource res;
2080 unsigned long base;
2081 const char *name;
2082 int ret, cs;
2083 u32 val;
2084 struct gpio_desc *waitpin_desc = NULL;
2085 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2086
2087 if (of_property_read_u32(child, "reg", &cs) < 0) {
2088 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2089 child);
2090 return -ENODEV;
2091 }
2092
2093 if (of_address_to_resource(child, 0, &res) < 0) {
2094 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2095 child);
2096 return -ENODEV;
2097 }
2098
2099 /*
2100 * Check if we have multiple instances of the same device
2101 * on a single chip select. If so, use the already initialized
2102 * timings.
2103 */
2104 name = gpmc_cs_get_name(cs);
2105 if (name && of_node_name_eq(child, name))
2106 goto no_timings;
2107
2108 ret = gpmc_cs_request(cs, resource_size(&res), &base);
2109 if (ret < 0) {
2110 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2111 return ret;
2112 }
2113 gpmc_cs_set_name(cs, child->full_name);
2114
2115 gpmc_read_settings_dt(child, &gpmc_s);
2116 gpmc_read_timings_dt(child, &gpmc_t);
2117
2118 /*
2119 * For some GPMC devices we still need to rely on the bootloader
2120 * timings because the devices can be connected via FPGA.
2121 * REVISIT: Add timing support from slls644g.pdf.
2122 */
2123 if (!gpmc_t.cs_rd_off) {
2124 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2125 cs);
2126 gpmc_cs_show_timings(cs,
2127 "please add GPMC bootloader timings to .dts");
2128 goto no_timings;
2129 }
2130
2131 /* CS must be disabled while making changes to gpmc configuration */
2132 gpmc_cs_disable_mem(cs);
2133
2134 /*
2135 * FIXME: gpmc_cs_request() will map the CS to an arbitrary
2136 * location in the gpmc address space. When booting with
2137 * device-tree we want the NOR flash to be mapped to the
2138 * location specified in the device-tree blob. So remap the
2139 * CS to this location. Once DT migration is complete should
2140 * just make gpmc_cs_request() map a specific address.
2141 */
2142 ret = gpmc_cs_remap(cs, res.start);
2143 if (ret < 0) {
2144 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2145 cs, &res.start);
2146 if (res.start < GPMC_MEM_START) {
2147 dev_info(&pdev->dev,
2148 "GPMC CS %d start cannot be lesser than 0x%x\n",
2149 cs, GPMC_MEM_START);
2150 } else if (res.end > GPMC_MEM_END) {
2151 dev_info(&pdev->dev,
2152 "GPMC CS %d end cannot be greater than 0x%x\n",
2153 cs, GPMC_MEM_END);
2154 }
2155 goto err;
2156 }
2157
2158 if (of_node_name_eq(child, "nand")) {
2159 /* Warn about older DT blobs with no compatible property */
2160 if (!of_property_read_bool(child, "compatible")) {
2161 dev_warn(&pdev->dev,
2162 "Incompatible NAND node: missing compatible");
2163 ret = -EINVAL;
2164 goto err;
2165 }
2166 }
2167
2168 if (of_node_name_eq(child, "onenand")) {
2169 /* Warn about older DT blobs with no compatible property */
2170 if (!of_property_read_bool(child, "compatible")) {
2171 dev_warn(&pdev->dev,
2172 "Incompatible OneNAND node: missing compatible");
2173 ret = -EINVAL;
2174 goto err;
2175 }
2176 }
2177
2178 if (of_device_is_compatible(child, "ti,omap2-nand")) {
2179 /* NAND specific setup */
2180 val = 8;
2181 of_property_read_u32(child, "nand-bus-width", &val);
2182 switch (val) {
2183 case 8:
2184 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2185 break;
2186 case 16:
2187 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2188 break;
2189 default:
2190 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2191 child);
2192 ret = -EINVAL;
2193 goto err;
2194 }
2195
2196 /* disable write protect */
2197 gpmc_configure(GPMC_CONFIG_WP, 0);
2198 gpmc_s.device_nand = true;
2199 } else {
2200 ret = of_property_read_u32(child, "bank-width",
2201 &gpmc_s.device_width);
2202 if (ret < 0 && !gpmc_s.device_width) {
2203 dev_err(&pdev->dev,
2204 "%pOF has no 'gpmc,device-width' property\n",
2205 child);
2206 goto err;
2207 }
2208 }
2209
2210 /* Reserve wait pin if it is required and valid */
2211 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2212 unsigned int wait_pin = gpmc_s.wait_pin;
2213
2214 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2215 wait_pin, "WAITPIN",
2216 GPIO_ACTIVE_HIGH,
2217 GPIOD_IN);
2218 if (IS_ERR(waitpin_desc)) {
2219 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2220 ret = PTR_ERR(waitpin_desc);
2221 goto err;
2222 }
2223 }
2224
2225 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2226
2227 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2228 if (ret < 0)
2229 goto err_cs;
2230
2231 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2232 if (ret) {
2233 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2234 child);
2235 goto err_cs;
2236 }
2237
2238 /* Clear limited address i.e. enable A26-A11 */
2239 val = gpmc_read_reg(GPMC_CONFIG);
2240 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2241 gpmc_write_reg(GPMC_CONFIG, val);
2242
2243 /* Enable CS region */
2244 gpmc_cs_enable_mem(cs);
2245
2246 no_timings:
2247
2248 /* create platform device, NULL on error or when disabled */
2249 if (!of_platform_device_create(child, NULL, &pdev->dev))
2250 goto err_child_fail;
2251
2252 /* is child a common bus? */
2253 if (of_match_node(of_default_bus_match_table, child))
2254 /* create children and other common bus children */
2255 if (of_platform_default_populate(child, NULL, &pdev->dev))
2256 goto err_child_fail;
2257
2258 return 0;
2259
2260 err_child_fail:
2261
2262 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2263 ret = -ENODEV;
2264
2265 err_cs:
2266 gpiochip_free_own_desc(waitpin_desc);
2267 err:
2268 gpmc_cs_free(cs);
2269
2270 return ret;
2271 }
2272
gpmc_probe_dt(struct platform_device * pdev)2273 static int gpmc_probe_dt(struct platform_device *pdev)
2274 {
2275 int ret;
2276 const struct of_device_id *of_id =
2277 of_match_device(gpmc_dt_ids, &pdev->dev);
2278
2279 if (!of_id)
2280 return 0;
2281
2282 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2283 &gpmc_cs_num);
2284 if (ret < 0) {
2285 pr_err("%s: number of chip-selects not defined\n", __func__);
2286 return ret;
2287 } else if (gpmc_cs_num < 1) {
2288 pr_err("%s: all chip-selects are disabled\n", __func__);
2289 return -EINVAL;
2290 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2291 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2292 __func__, GPMC_CS_NUM);
2293 return -EINVAL;
2294 }
2295
2296 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2297 &gpmc_nr_waitpins);
2298 if (ret < 0) {
2299 pr_err("%s: number of wait pins not found!\n", __func__);
2300 return ret;
2301 }
2302
2303 return 0;
2304 }
2305
gpmc_probe_dt_children(struct platform_device * pdev)2306 static void gpmc_probe_dt_children(struct platform_device *pdev)
2307 {
2308 int ret;
2309 struct device_node *child;
2310
2311 for_each_available_child_of_node(pdev->dev.of_node, child) {
2312 ret = gpmc_probe_generic_child(pdev, child);
2313 if (ret) {
2314 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2315 child, ret);
2316 }
2317 }
2318 }
2319 #else
gpmc_read_settings_dt(struct device_node * np,struct gpmc_settings * p)2320 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2321 {
2322 memset(p, 0, sizeof(*p));
2323 }
gpmc_probe_dt(struct platform_device * pdev)2324 static int gpmc_probe_dt(struct platform_device *pdev)
2325 {
2326 return 0;
2327 }
2328
gpmc_probe_dt_children(struct platform_device * pdev)2329 static void gpmc_probe_dt_children(struct platform_device *pdev)
2330 {
2331 }
2332 #endif /* CONFIG_OF */
2333
gpmc_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)2334 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2335 {
2336 return 1; /* we're input only */
2337 }
2338
gpmc_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)2339 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2340 unsigned int offset)
2341 {
2342 return 0; /* we're input only */
2343 }
2344
gpmc_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)2345 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2346 unsigned int offset, int value)
2347 {
2348 return -EINVAL; /* we're input only */
2349 }
2350
gpmc_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)2351 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2352 int value)
2353 {
2354 }
2355
gpmc_gpio_get(struct gpio_chip * chip,unsigned int offset)2356 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2357 {
2358 u32 reg;
2359
2360 offset += 8;
2361
2362 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2363
2364 return !!reg;
2365 }
2366
gpmc_gpio_init(struct gpmc_device * gpmc)2367 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2368 {
2369 int ret;
2370
2371 gpmc->gpio_chip.parent = gpmc->dev;
2372 gpmc->gpio_chip.owner = THIS_MODULE;
2373 gpmc->gpio_chip.label = DEVICE_NAME;
2374 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2375 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2376 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2377 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2378 gpmc->gpio_chip.set = gpmc_gpio_set;
2379 gpmc->gpio_chip.get = gpmc_gpio_get;
2380 gpmc->gpio_chip.base = -1;
2381
2382 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2383 if (ret < 0) {
2384 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2385 return ret;
2386 }
2387
2388 return 0;
2389 }
2390
omap3_gpmc_save_context(struct gpmc_device * gpmc)2391 static void omap3_gpmc_save_context(struct gpmc_device *gpmc)
2392 {
2393 struct omap3_gpmc_regs *gpmc_context;
2394 int i;
2395
2396 if (!gpmc || !gpmc_base)
2397 return;
2398
2399 gpmc_context = &gpmc->context;
2400
2401 gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2402 gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2403 gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2404 gpmc_context->config = gpmc_read_reg(GPMC_CONFIG);
2405 gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2406 gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2407 gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2408 for (i = 0; i < gpmc_cs_num; i++) {
2409 gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2410 if (gpmc_context->cs_context[i].is_valid) {
2411 gpmc_context->cs_context[i].config1 =
2412 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2413 gpmc_context->cs_context[i].config2 =
2414 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2415 gpmc_context->cs_context[i].config3 =
2416 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2417 gpmc_context->cs_context[i].config4 =
2418 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2419 gpmc_context->cs_context[i].config5 =
2420 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2421 gpmc_context->cs_context[i].config6 =
2422 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2423 gpmc_context->cs_context[i].config7 =
2424 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2425 }
2426 }
2427 }
2428
omap3_gpmc_restore_context(struct gpmc_device * gpmc)2429 static void omap3_gpmc_restore_context(struct gpmc_device *gpmc)
2430 {
2431 struct omap3_gpmc_regs *gpmc_context;
2432 int i;
2433
2434 if (!gpmc || !gpmc_base)
2435 return;
2436
2437 gpmc_context = &gpmc->context;
2438
2439 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig);
2440 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable);
2441 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl);
2442 gpmc_write_reg(GPMC_CONFIG, gpmc_context->config);
2443 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1);
2444 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2);
2445 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control);
2446 for (i = 0; i < gpmc_cs_num; i++) {
2447 if (gpmc_context->cs_context[i].is_valid) {
2448 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2449 gpmc_context->cs_context[i].config1);
2450 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2451 gpmc_context->cs_context[i].config2);
2452 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2453 gpmc_context->cs_context[i].config3);
2454 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2455 gpmc_context->cs_context[i].config4);
2456 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2457 gpmc_context->cs_context[i].config5);
2458 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2459 gpmc_context->cs_context[i].config6);
2460 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2461 gpmc_context->cs_context[i].config7);
2462 } else {
2463 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0);
2464 }
2465 }
2466 }
2467
omap_gpmc_context_notifier(struct notifier_block * nb,unsigned long cmd,void * v)2468 static int omap_gpmc_context_notifier(struct notifier_block *nb,
2469 unsigned long cmd, void *v)
2470 {
2471 struct gpmc_device *gpmc;
2472
2473 gpmc = container_of(nb, struct gpmc_device, nb);
2474 if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev))
2475 return NOTIFY_OK;
2476
2477 switch (cmd) {
2478 case CPU_CLUSTER_PM_ENTER:
2479 omap3_gpmc_save_context(gpmc);
2480 break;
2481 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
2482 break;
2483 case CPU_CLUSTER_PM_EXIT:
2484 omap3_gpmc_restore_context(gpmc);
2485 break;
2486 }
2487
2488 return NOTIFY_OK;
2489 }
2490
gpmc_probe(struct platform_device * pdev)2491 static int gpmc_probe(struct platform_device *pdev)
2492 {
2493 int rc;
2494 u32 l;
2495 struct resource *res;
2496 struct gpmc_device *gpmc;
2497
2498 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2499 if (!gpmc)
2500 return -ENOMEM;
2501
2502 gpmc->dev = &pdev->dev;
2503 platform_set_drvdata(pdev, gpmc);
2504
2505 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2506 if (!res)
2507 return -ENOENT;
2508
2509 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2510 if (IS_ERR(gpmc_base))
2511 return PTR_ERR(gpmc_base);
2512
2513 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2514 if (!res) {
2515 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2516 return -ENOENT;
2517 }
2518
2519 gpmc->irq = res->start;
2520
2521 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2522 if (IS_ERR(gpmc_l3_clk)) {
2523 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2524 return PTR_ERR(gpmc_l3_clk);
2525 }
2526
2527 if (!clk_get_rate(gpmc_l3_clk)) {
2528 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2529 return -EINVAL;
2530 }
2531
2532 if (pdev->dev.of_node) {
2533 rc = gpmc_probe_dt(pdev);
2534 if (rc)
2535 return rc;
2536 } else {
2537 gpmc_cs_num = GPMC_CS_NUM;
2538 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2539 }
2540
2541 pm_runtime_enable(&pdev->dev);
2542 pm_runtime_get_sync(&pdev->dev);
2543
2544 l = gpmc_read_reg(GPMC_REVISION);
2545
2546 /*
2547 * FIXME: Once device-tree migration is complete the below flags
2548 * should be populated based upon the device-tree compatible
2549 * string. For now just use the IP revision. OMAP3+ devices have
2550 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2551 * devices support the addr-addr-data multiplex protocol.
2552 *
2553 * GPMC IP revisions:
2554 * - OMAP24xx = 2.0
2555 * - OMAP3xxx = 5.0
2556 * - OMAP44xx/54xx/AM335x = 6.0
2557 */
2558 if (GPMC_REVISION_MAJOR(l) > 0x4)
2559 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2560 if (GPMC_REVISION_MAJOR(l) > 0x5)
2561 gpmc_capability |= GPMC_HAS_MUX_AAD;
2562 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2563 GPMC_REVISION_MINOR(l));
2564
2565 gpmc_mem_init();
2566 rc = gpmc_gpio_init(gpmc);
2567 if (rc)
2568 goto gpio_init_failed;
2569
2570 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2571 rc = gpmc_setup_irq(gpmc);
2572 if (rc) {
2573 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2574 goto gpio_init_failed;
2575 }
2576
2577 gpmc_probe_dt_children(pdev);
2578
2579 gpmc->nb.notifier_call = omap_gpmc_context_notifier;
2580 cpu_pm_register_notifier(&gpmc->nb);
2581
2582 return 0;
2583
2584 gpio_init_failed:
2585 gpmc_mem_exit();
2586 pm_runtime_put_sync(&pdev->dev);
2587 pm_runtime_disable(&pdev->dev);
2588
2589 return rc;
2590 }
2591
gpmc_remove(struct platform_device * pdev)2592 static int gpmc_remove(struct platform_device *pdev)
2593 {
2594 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2595
2596 cpu_pm_unregister_notifier(&gpmc->nb);
2597 gpmc_free_irq(gpmc);
2598 gpmc_mem_exit();
2599 pm_runtime_put_sync(&pdev->dev);
2600 pm_runtime_disable(&pdev->dev);
2601
2602 return 0;
2603 }
2604
2605 #ifdef CONFIG_PM_SLEEP
gpmc_suspend(struct device * dev)2606 static int gpmc_suspend(struct device *dev)
2607 {
2608 struct gpmc_device *gpmc = dev_get_drvdata(dev);
2609
2610 omap3_gpmc_save_context(gpmc);
2611 pm_runtime_put_sync(dev);
2612 gpmc->is_suspended = 1;
2613
2614 return 0;
2615 }
2616
gpmc_resume(struct device * dev)2617 static int gpmc_resume(struct device *dev)
2618 {
2619 struct gpmc_device *gpmc = dev_get_drvdata(dev);
2620
2621 pm_runtime_get_sync(dev);
2622 omap3_gpmc_restore_context(gpmc);
2623 gpmc->is_suspended = 0;
2624
2625 return 0;
2626 }
2627 #endif
2628
2629 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2630
2631 static struct platform_driver gpmc_driver = {
2632 .probe = gpmc_probe,
2633 .remove = gpmc_remove,
2634 .driver = {
2635 .name = DEVICE_NAME,
2636 .of_match_table = of_match_ptr(gpmc_dt_ids),
2637 .pm = &gpmc_pm_ops,
2638 },
2639 };
2640
gpmc_init(void)2641 static __init int gpmc_init(void)
2642 {
2643 return platform_driver_register(&gpmc_driver);
2644 }
2645 postcore_initcall(gpmc_init);
2646
