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Searched refs:GENMASK_ULL (Results 1 – 25 of 200) sorted by relevance

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/Linux-v5.15/drivers/infiniband/hw/irdma/
Ddefs.h372 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
373 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
374 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
375 #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
376 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
377 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
378 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
379 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
380 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
382 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
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Duda_d.h19 #define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
20 #define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
21 #define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42)
25 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
26 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16)
27 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)
29 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
31 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
33 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
35 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
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Dicrdma_hw.h54 #define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)
56 #define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)
58 #define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)
60 #define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)
/Linux-v5.15/drivers/iommu/arm/arm-smmu-v3/
Darm-smmu-v3.h128 #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
158 #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
178 #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
200 #define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0)
201 #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
205 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
211 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)
214 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
215 #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
217 #define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0)
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/Linux-v5.15/drivers/net/ethernet/marvell/octeontx2/af/
Dcgx_fw_if.h170 #define EVTREG_ID GENMASK_ULL(8, 3)
177 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
182 #define RESP_MAJOR_VER GENMASK_ULL(12, 9)
183 #define RESP_MINOR_VER GENMASK_ULL(16, 13)
188 #define RESP_MAC_ADDR GENMASK_ULL(56, 9)
193 #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)
198 #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)
203 #define RESP_FWD_BASE GENMASK_ULL(56, 9)
204 #define RESP_LINKSTAT_LMAC_TYPE GENMASK_ULL(35, 28)
228 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
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Dnpc.h380 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)
383 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)
385 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)
387 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7)
389 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10)
391 #define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13)
393 #define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16)
395 #define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19)
397 #define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22)
399 #define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(26, 25)
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/Linux-v5.15/drivers/platform/mellanox/
Dmlxbf-tmfifo-regs.h18 #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
19 #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
25 #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
26 #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
30 #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
31 #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
35 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
36 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
43 #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
44 #define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)
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/Linux-v5.15/drivers/mmc/host/
Dcavium.h121 #define MIO_EMM_DMA_FIFO_CFG_INT_LVL GENMASK_ULL(12, 8)
122 #define MIO_EMM_DMA_FIFO_CFG_COUNT GENMASK_ULL(4, 0)
130 #define MIO_EMM_DMA_FIFO_CMD_SIZE GENMASK_ULL(55, 36)
133 #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60)
136 #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49)
137 #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41)
138 #define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38)
139 #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32)
140 #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0)
143 #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60)
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/Linux-v5.15/tools/perf/util/arm-spe-decoder/
Darm-spe-pkt-decoder.h44 #define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
48 #define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)
54 #define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)
59 #define SPE_HDR_SHORT_INDEX(h) ((h) & GENMASK_ULL(2, 0))
60 #define SPE_HDR_EXTENDED_INDEX(h0, h1) (((h0) & GENMASK_ULL(1, 0)) << 3 | \
71 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))
72 #define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48)
75 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
77 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56)
85 #define SPE_CTX_PKT_HDR_INDEX(h) ((h) & GENMASK_ULL(1, 0))
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/Linux-v5.15/drivers/fpga/
Ddfl.h71 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
74 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
75 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
77 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
83 #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
96 #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
102 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
103 #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
104 #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
105 #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
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Ddfl-fme-perf.c31 #define CACHE_CTRL_EVNT GENMASK_ULL(19, 16)
49 #define CACHE_CNTR_EVNT_CNTR GENMASK_ULL(47, 0)
50 #define CACHE_CNTR_EVNT GENMASK_ULL(63, 60)
60 #define FAB_CTRL_EVNT GENMASK_ULL(19, 16)
70 #define FAB_PORT_ID GENMASK_ULL(21, 20)
75 #define FAB_CNTR_EVNT_CNTR GENMASK_ULL(59, 0)
76 #define FAB_CNTR_EVNT GENMASK_ULL(63, 60)
95 #define VTD_CTRL_EVNT GENMASK_ULL(19, 16)
105 #define VTD_CNTR_EVNT_CNTR GENMASK_ULL(47, 0)
106 #define VTD_CNTR_EVNT GENMASK_ULL(63, 60)
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/Linux-v5.15/drivers/iommu/intel/
Dcap_audit.h18 #define CAP_MAMV_MASK GENMASK_ULL(53, 48)
19 #define CAP_NFR_MASK GENMASK_ULL(47, 40)
21 #define CAP_SLLPS_MASK GENMASK_ULL(37, 34)
22 #define CAP_FRO_MASK GENMASK_ULL(33, 24)
24 #define CAP_MGAW_MASK GENMASK_ULL(21, 16)
25 #define CAP_SAGAW_MASK GENMASK_ULL(12, 8)
31 #define CAP_NDOMS_MASK GENMASK_ULL(2, 0)
46 #define ECAP_PSS_MASK GENMASK_ULL(39, 35)
54 #define ECAP_MHMV_MASK GENMASK_ULL(23, 20)
55 #define ECAP_IRO_MASK GENMASK_ULL(17, 8)
/Linux-v5.15/lib/
Dtest_bits.c29 KUNIT_EXPECT_EQ(test, 1ull, GENMASK_ULL(0, 0)); in genmask_ull_test()
30 KUNIT_EXPECT_EQ(test, 3ull, GENMASK_ULL(1, 0)); in genmask_ull_test()
31 KUNIT_EXPECT_EQ(test, 0x000000ffffe00000ull, GENMASK_ULL(39, 21)); in genmask_ull_test()
32 KUNIT_EXPECT_EQ(test, 0xffffffffffffffffull, GENMASK_ULL(63, 0)); in genmask_ull_test()
36 GENMASK_ULL(0, 1); in genmask_ull_test()
37 GENMASK_ULL(0, 10); in genmask_ull_test()
38 GENMASK_ULL(9, 10); in genmask_ull_test()
/Linux-v5.15/include/linux/irqchip/
Darm-gic-v3.h171 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
197 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
198 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
246 #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
247 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
249 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
250 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
251 #define GICR_INVLPIR_V GENMASK_ULL(63, 63)
298 #define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)
300 #define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53)
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/Linux-v5.15/arch/arm64/kvm/vgic/
Dvgic.h72 #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
75 #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
76 #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
80 #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
82 #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
83 #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
86 #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
88 #define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0)
89 #define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12)
91 #define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16)
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/Linux-v5.15/drivers/firmware/efi/
Dcper-x86.c13 #define VALID_PROC_ERR_INFO_NUM(bits) (((bits) & GENMASK_ULL(7, 2)) >> 2)
14 #define VALID_PROC_CXT_INFO_NUM(bits) (((bits) & GENMASK_ULL(13, 8)) >> 8)
48 #define CHECK_VALID_BITS(check) (((check) & GENMASK_ULL(15, 0)))
49 #define CHECK_TRANS_TYPE(check) (((check) & GENMASK_ULL(17, 16)) >> 16)
50 #define CHECK_OPERATION(check) (((check) & GENMASK_ULL(21, 18)) >> 18)
51 #define CHECK_LEVEL(check) (((check) & GENMASK_ULL(24, 22)) >> 22)
58 #define CHECK_BUS_PART_TYPE(check) (((check) & GENMASK_ULL(31, 30)) >> 30)
60 #define CHECK_BUS_ADDR_SPACE(check) (((check) & GENMASK_ULL(34, 33)) >> 33)
69 #define CHECK_MS_ERR_TYPE(check) (((check) & GENMASK_ULL(18, 16)) >> 16)
/Linux-v5.15/drivers/gpu/drm/i915/
Di915_buddy.h14 #define I915_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
15 #define I915_BUDDY_HEADER_STATE GENMASK_ULL(11, 10)
20 #define I915_BUDDY_HEADER_UNUSED GENMASK_ULL(9, 6)
21 #define I915_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0)
/Linux-v5.15/drivers/spi/
Dspi-altera-dfl.c32 #define DATA_WIDTH GENMASK_ULL(7, 2)
33 #define NUM_CHIPSELECT GENMASK_ULL(13, 8)
36 #define PERIPHERAL_ID GENMASK_ULL(47, 32)
37 #define SPI_CLK GENMASK_ULL(31, 22)
44 #define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
/Linux-v5.15/include/linux/i3c/
Ddevice.h79 #define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33)
81 #define I3C_PID_RND_VAL(pid) ((pid) & GENMASK_ULL(31, 0))
82 #define I3C_PID_PART_ID(pid) (((pid) & GENMASK_ULL(31, 16)) >> 16)
83 #define I3C_PID_INSTANCE_ID(pid) (((pid) & GENMASK_ULL(15, 12)) >> 12)
84 #define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0))
/Linux-v5.15/drivers/cxl/
Dcxl.h55 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
56 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
71 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
72 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
74 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
/Linux-v5.15/drivers/net/ethernet/netronome/nfp/nfpcore/
Dnfp_nsp_eth.c24 #define NSP_ETH_PORT_LANES GENMASK_ULL(3, 0)
25 #define NSP_ETH_PORT_INDEX GENMASK_ULL(15, 8)
26 #define NSP_ETH_PORT_LABEL GENMASK_ULL(53, 48)
27 #define NSP_ETH_PORT_PHYLABEL GENMASK_ULL(59, 54)
37 #define NSP_ETH_STATE_RATE GENMASK_ULL(11, 8)
38 #define NSP_ETH_STATE_INTERFACE GENMASK_ULL(19, 12)
39 #define NSP_ETH_STATE_MEDIA GENMASK_ULL(21, 20)
41 #define NSP_ETH_STATE_ANEG GENMASK_ULL(25, 23)
42 #define NSP_ETH_STATE_FEC GENMASK_ULL(27, 26)
Dnfp_nsp.c31 #define NSP_STATUS_MAGIC GENMASK_ULL(63, 48)
32 #define NSP_STATUS_MAJOR GENMASK_ULL(47, 44)
33 #define NSP_STATUS_MINOR GENMASK_ULL(43, 32)
34 #define NSP_STATUS_CODE GENMASK_ULL(31, 16)
35 #define NSP_STATUS_RESULT GENMASK_ULL(15, 8)
39 #define NSP_COMMAND_OPTION GENMASK_ULL(63, 32)
40 #define NSP_COMMAND_CODE GENMASK_ULL(31, 16)
46 #define NSP_BUFFER_CPP GENMASK_ULL(63, 40)
47 #define NSP_BUFFER_ADDRESS GENMASK_ULL(39, 0)
50 #define NSP_DFLT_BUFFER_CPP GENMASK_ULL(63, 40)
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/Linux-v5.15/arch/x86/include/asm/
Dsgx.h79 #define SGX_MISC_RESERVED_MASK GENMASK_ULL(63, 1)
105 #define SGX_ATTR_RESERVED_MASK (BIT_ULL(3) | BIT_ULL(6) | GENMASK_ULL(63, 8))
157 #define SGX_TCS_RESERVED_MASK GENMASK_ULL(63, 1)
253 #define SGX_SECINFO_PERMISSION_MASK GENMASK_ULL(2, 0)
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_debugfs.c167 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; in amdgpu_debugfs_process_reg_op()
168 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; in amdgpu_debugfs_process_reg_op()
169 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; in amdgpu_debugfs_process_reg_op()
180 me = (*pos & GENMASK_ULL(33, 24)) >> 24; in amdgpu_debugfs_process_reg_op()
181 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; in amdgpu_debugfs_process_reg_op()
182 queue = (*pos & GENMASK_ULL(53, 44)) >> 44; in amdgpu_debugfs_process_reg_op()
183 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54; in amdgpu_debugfs_process_reg_op()
836 offset = (*pos & GENMASK_ULL(6, 0)); in amdgpu_debugfs_wave_read()
837 se = (*pos & GENMASK_ULL(14, 7)) >> 7; in amdgpu_debugfs_wave_read()
838 sh = (*pos & GENMASK_ULL(22, 15)) >> 15; in amdgpu_debugfs_wave_read()
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/Linux-v5.15/arch/mips/include/asm/
Dmips-cm.h132 #define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32)
139 #define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15)
175 #define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58)
276 #define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48)
277 #define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6)

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