Searched refs:EXYNOS_I2S_BUS (Results 1 – 10 of 10) sorted by relevance
19 #define EXYNOS_I2S_BUS 6 macro
221 clocks = <&clock_audss EXYNOS_I2S_BUS>,222 <&clock_audss EXYNOS_I2S_BUS>,
550 assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
599 clocks = <&clock_audss EXYNOS_I2S_BUS>,600 <&clock_audss EXYNOS_I2S_BUS>,
528 assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
504 clocks = <&clock_audss EXYNOS_I2S_BUS>,505 <&clock_audss EXYNOS_I2S_BUS>,
713 assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
80 clocks = <&clock_audss EXYNOS_I2S_BUS>,
694 assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
218 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", in exynos_audss_clk_probe()
