ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (reference) in projects: Linux-v5.15

Searched refs:ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/radeon/
D	nid.h	`108 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro`
D	ni.c	`1284 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE \| in cayman_pcie_gart_enable() 1363 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE \| in cayman_pcie_gart_disable()`
D	sid.h	`375 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro`
D	cikd.h	`493 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro`
D	si.c	`4303 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE \| in si_pcie_gart_enable() 4389 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE \| in si_pcie_gart_disable()`
D	cik.c	`5442 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE \| in cik_pcie_gart_enable() 5559 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE \| in cik_pcie_gart_disable()`
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
D	gmc_v7_0.c	`642 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()`
D	gmc_v8_0.c	`859 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()`
D	sid.h	`376 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro`