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Searched refs:DSPCNTR (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/display/
Di9xx_plane.c485 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_update_plane()
518 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_disable_plane()
543 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in g4x_primary_async_flip()
670 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
988 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
Dintel_display.c5114 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_pipe_color_config()
12718 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & in i830_disable_pipe()
12721 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & in i830_disable_pipe()
12724 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & in i830_disable_pipe()
/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Ddisplay.c188 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
499 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
Dfb_decoder.c213 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
Dhandlers.c1018 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()
2335 MMIO_D(DSPCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
2346 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
2357 MMIO_D(DSPCNTR(PIPE_C), D_ALL); in init_generic_mmio_info()
Dcmd_parser.c1312 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()
1378 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
/Linux-v5.15/drivers/gpu/drm/i915/
Dintel_pm.c7242 intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe), in g4x_disable_trickle_feed()
7243 intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) | in g4x_disable_trickle_feed()
Di915_reg.h6760 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) macro