Searched refs:DRD (Results 1 – 8 of 8) sorted by relevance
8 icfg - for DRD ICFG configurations9 rst-ctrl - for DRD IDM reset
141 Samsung Exynos5 SoC series USB DRD PHY controller150 - reg : Register offset and length of USB DRD PHY register set;154 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),185 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
80 tristate "Exynos5 SoC series USB DRD PHY driver"88 Enable USB DRD PHY support for Exynos 5 SoC series.89 This driver provides PHY interface for USB 3.0 DRD controller
54 u32 DRD; /* (u32*) address of self-modified DRD */ member231 var->DRD = bcom_sram_va2pa(self_modified_drd(tsk->tasknum)); in bcom_fec_tx_reset()
69 tristate "Broadcom Northstar2 USB DRD PHY support"75 Enable this to support the Broadcom Northstar2 USB DRD PHY.
4 tristate "DesignWare USB2 DRD Core Support"
4 tristate "DesignWare USB3 DRD Core Support"
4084 CADENCE USB3 DRD IP DRIVER4096 CADENCE USBSSP DRD IP DRIVER5357 DESIGNWARE USB2 DRD IP DRIVER5364 DESIGNWARE USB3 DRD IP DRIVER11894 MEDIATEK USB3 DRD IP DRIVER
