1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
3  */
4 
5 #ifndef _DPU_HW_CATALOG_H
6 #define _DPU_HW_CATALOG_H
7 
8 #include <linux/kernel.h>
9 #include <linux/bug.h>
10 #include <linux/bitmap.h>
11 #include <linux/err.h>
12 
13 /**
14  * Max hardware block count: For ex: max 12 SSPP pipes or
15  * 5 ctl paths. In all cases, it can have max 12 hardware blocks
16  * based on current design
17  */
18 #define MAX_BLOCKS    12
19 
20 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28)    |\
21 		((MINOR & 0xFFF) << 16)  |\
22 		(STEP & 0xFFFF))
23 
24 #define DPU_HW_MAJOR(rev)		((rev) >> 28)
25 #define DPU_HW_MINOR(rev)		(((rev) >> 16) & 0xFFF)
26 #define DPU_HW_STEP(rev)		((rev) & 0xFFFF)
27 #define DPU_HW_MAJOR_MINOR(rev)		((rev) >> 16)
28 
29 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2)   \
30 	(DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2)))
31 
32 #define DPU_HW_VER_170	DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */
33 #define DPU_HW_VER_171	DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */
34 #define DPU_HW_VER_172	DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */
35 #define DPU_HW_VER_300	DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */
36 #define DPU_HW_VER_301	DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */
37 #define DPU_HW_VER_400	DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */
38 #define DPU_HW_VER_401	DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */
39 #define DPU_HW_VER_410	DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
40 #define DPU_HW_VER_500	DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */
41 #define DPU_HW_VER_501	DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */
42 #define DPU_HW_VER_600	DPU_HW_VER(6, 0, 0) /* sm8250 */
43 #define DPU_HW_VER_620	DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
44 #define DPU_HW_VER_720	DPU_HW_VER(7, 2, 0) /* sc7280 */
45 
46 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
47 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
48 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400)
49 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410)
50 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500)
51 #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620)
52 #define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720)
53 
54 #define DPU_HW_BLK_NAME_LEN	16
55 
56 #define MAX_IMG_WIDTH 0x3fff
57 #define MAX_IMG_HEIGHT 0x3fff
58 
59 #define CRTC_DUAL_MIXERS	2
60 
61 #define MAX_XIN_COUNT 16
62 
63 /**
64  * Supported UBWC feature versions
65  */
66 enum {
67 	DPU_HW_UBWC_VER_10 = 0x100,
68 	DPU_HW_UBWC_VER_20 = 0x200,
69 	DPU_HW_UBWC_VER_30 = 0x300,
70 	DPU_HW_UBWC_VER_40 = 0x400,
71 };
72 
73 /**
74  * MDP TOP BLOCK features
75  * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
76  * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
77  * @DPU_MDP_BWC,           MDSS HW supports Bandwidth compression.
78  * @DPU_MDP_UBWC_1_0,      This chipsets supports Universal Bandwidth
79  *                         compression initial revision
80  * @DPU_MDP_UBWC_1_5,      Universal Bandwidth compression version 1.5
81  * @DPU_MDP_MAX            Maximum value
82 
83  */
84 enum {
85 	DPU_MDP_PANIC_PER_PIPE = 0x1,
86 	DPU_MDP_10BIT_SUPPORT,
87 	DPU_MDP_BWC,
88 	DPU_MDP_UBWC_1_0,
89 	DPU_MDP_UBWC_1_5,
90 	DPU_MDP_MAX
91 };
92 
93 /**
94  * SSPP sub-blocks/features
95  * @DPU_SSPP_SRC             Src and fetch part of the pipes,
96  * @DPU_SSPP_SCALER_QSEED2,  QSEED2 algorithm support
97  * @DPU_SSPP_SCALER_QSEED3,  QSEED3 alogorithm support
98  * @DPU_SSPP_SCALER_QSEED3LITE,  QSEED3 Lite alogorithm support
99  * @DPU_SSPP_SCALER_QSEED4,  QSEED4 algorithm support
100  * @DPU_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes
101  * @DPU_SSPP_CSC,            Support of Color space converion
102  * @DPU_SSPP_CSC_10BIT,      Support of 10-bit Color space conversion
103  * @DPU_SSPP_CURSOR,         SSPP can be used as a cursor layer
104  * @DPU_SSPP_QOS,            SSPP support QoS control, danger/safe/creq
105  * @DPU_SSPP_QOS_8LVL,       SSPP support 8-level QoS control
106  * @DPU_SSPP_EXCL_RECT,      SSPP supports exclusion rect
107  * @DPU_SSPP_SMART_DMA_V1,   SmartDMA 1.0 support
108  * @DPU_SSPP_SMART_DMA_V2,   SmartDMA 2.0 support
109  * @DPU_SSPP_TS_PREFILL      Supports prefill with traffic shaper
110  * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
111  * @DPU_SSPP_CDP             Supports client driven prefetch
112  * @DPU_SSPP_MAX             maximum value
113  */
114 enum {
115 	DPU_SSPP_SRC = 0x1,
116 	DPU_SSPP_SCALER_QSEED2,
117 	DPU_SSPP_SCALER_QSEED3,
118 	DPU_SSPP_SCALER_QSEED3LITE,
119 	DPU_SSPP_SCALER_QSEED4,
120 	DPU_SSPP_SCALER_RGB,
121 	DPU_SSPP_CSC,
122 	DPU_SSPP_CSC_10BIT,
123 	DPU_SSPP_CURSOR,
124 	DPU_SSPP_QOS,
125 	DPU_SSPP_QOS_8LVL,
126 	DPU_SSPP_EXCL_RECT,
127 	DPU_SSPP_SMART_DMA_V1,
128 	DPU_SSPP_SMART_DMA_V2,
129 	DPU_SSPP_TS_PREFILL,
130 	DPU_SSPP_TS_PREFILL_REC1,
131 	DPU_SSPP_CDP,
132 	DPU_SSPP_MAX
133 };
134 
135 /*
136  * MIXER sub-blocks/features
137  * @DPU_MIXER_LAYER           Layer mixer layer blend configuration,
138  * @DPU_MIXER_SOURCESPLIT     Layer mixer supports source-split configuration
139  * @DPU_MIXER_GC              Gamma correction block
140  * @DPU_DIM_LAYER             Layer mixer supports dim layer
141  * @DPU_MIXER_MAX             maximum value
142  */
143 enum {
144 	DPU_MIXER_LAYER = 0x1,
145 	DPU_MIXER_SOURCESPLIT,
146 	DPU_MIXER_GC,
147 	DPU_DIM_LAYER,
148 	DPU_MIXER_MAX
149 };
150 
151 /**
152  * DSPP sub-blocks
153  * @DPU_DSPP_PCC             Panel color correction block
154  * @DPU_DSPP_GC              Gamma correction block
155  */
156 enum {
157 	DPU_DSPP_PCC = 0x1,
158 	DPU_DSPP_GC,
159 	DPU_DSPP_MAX
160 };
161 
162 /**
163  * PINGPONG sub-blocks
164  * @DPU_PINGPONG_TE         Tear check block
165  * @DPU_PINGPONG_TE2        Additional tear check block for split pipes
166  * @DPU_PINGPONG_SPLIT      PP block supports split fifo
167  * @DPU_PINGPONG_SLAVE      PP block is a suitable slave for split fifo
168  * @DPU_PINGPONG_DITHER,    Dither blocks
169  * @DPU_PINGPONG_MAX
170  */
171 enum {
172 	DPU_PINGPONG_TE = 0x1,
173 	DPU_PINGPONG_TE2,
174 	DPU_PINGPONG_SPLIT,
175 	DPU_PINGPONG_SLAVE,
176 	DPU_PINGPONG_DITHER,
177 	DPU_PINGPONG_MAX
178 };
179 
180 /**
181  * CTL sub-blocks
182  * @DPU_CTL_SPLIT_DISPLAY       CTL supports video mode split display
183  * @DPU_CTL_MAX
184  */
185 enum {
186 	DPU_CTL_SPLIT_DISPLAY = 0x1,
187 	DPU_CTL_ACTIVE_CFG,
188 	DPU_CTL_FETCH_ACTIVE,
189 	DPU_CTL_MAX
190 };
191 
192 /**
193  * INTF sub-blocks
194  * @DPU_INTF_INPUT_CTRL         Supports the setting of pp block from which
195  *                              pixel data arrives to this INTF
196  * @DPU_INTF_TE                 INTF block has TE configuration support
197  * @DPU_DATA_HCTL_EN            Allows data to be transferred at different rate
198                                 than video timing
199  * @DPU_INTF_MAX
200  */
201 enum {
202 	DPU_INTF_INPUT_CTRL = 0x1,
203 	DPU_INTF_TE,
204 	DPU_DATA_HCTL_EN,
205 	DPU_INTF_MAX
206 };
207 
208 /**
209  * VBIF sub-blocks and features
210  * @DPU_VBIF_QOS_OTLIM        VBIF supports OT Limit
211  * @DPU_VBIF_QOS_REMAP        VBIF supports QoS priority remap
212  * @DPU_VBIF_MAX              maximum value
213  */
214 enum {
215 	DPU_VBIF_QOS_OTLIM = 0x1,
216 	DPU_VBIF_QOS_REMAP,
217 	DPU_VBIF_MAX
218 };
219 
220 /**
221  * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU
222  * @name:              string name for debug purposes
223  * @id:                enum identifying this block
224  * @base:              register base offset to mdss
225  * @len:               length of hardware block
226  * @features           bit mask identifying sub-blocks/features
227  */
228 #define DPU_HW_BLK_INFO \
229 	char name[DPU_HW_BLK_NAME_LEN]; \
230 	u32 id; \
231 	u32 base; \
232 	u32 len; \
233 	unsigned long features
234 
235 /**
236  * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU
237  * @name:              string name for debug purposes
238  * @id:                enum identifying this sub-block
239  * @base:              offset of this sub-block relative to the block
240  *                     offset
241  * @len                register block length of this sub-block
242  */
243 #define DPU_HW_SUBBLK_INFO \
244 	char name[DPU_HW_BLK_NAME_LEN]; \
245 	u32 id; \
246 	u32 base; \
247 	u32 len
248 
249 /**
250  * struct dpu_src_blk: SSPP part of the source pipes
251  * @info:   HW register and features supported by this sub-blk
252  */
253 struct dpu_src_blk {
254 	DPU_HW_SUBBLK_INFO;
255 };
256 
257 /**
258  * struct dpu_scaler_blk: Scaler information
259  * @info:   HW register and features supported by this sub-blk
260  * @version: qseed block revision
261  */
262 struct dpu_scaler_blk {
263 	DPU_HW_SUBBLK_INFO;
264 	u32 version;
265 };
266 
267 struct dpu_csc_blk {
268 	DPU_HW_SUBBLK_INFO;
269 };
270 
271 /**
272  * struct dpu_pp_blk : Pixel processing sub-blk information
273  * @info:   HW register and features supported by this sub-blk
274  * @version: HW Algorithm version
275  */
276 struct dpu_pp_blk {
277 	DPU_HW_SUBBLK_INFO;
278 	u32 version;
279 };
280 
281 /**
282  * enum dpu_qos_lut_usage - define QoS LUT use cases
283  */
284 enum dpu_qos_lut_usage {
285 	DPU_QOS_LUT_USAGE_LINEAR,
286 	DPU_QOS_LUT_USAGE_MACROTILE,
287 	DPU_QOS_LUT_USAGE_NRT,
288 	DPU_QOS_LUT_USAGE_MAX,
289 };
290 
291 /**
292  * struct dpu_qos_lut_entry - define QoS LUT table entry
293  * @fl: fill level, or zero on last entry to indicate default lut
294  * @lut: lut to use if equal to or less than fill level
295  */
296 struct dpu_qos_lut_entry {
297 	u32 fl;
298 	u64 lut;
299 };
300 
301 /**
302  * struct dpu_qos_lut_tbl - define QoS LUT table
303  * @nentry: number of entry in this table
304  * @entries: Pointer to table entries
305  */
306 struct dpu_qos_lut_tbl {
307 	u32 nentry;
308 	const struct dpu_qos_lut_entry *entries;
309 };
310 
311 /**
312  * struct dpu_caps - define DPU capabilities
313  * @max_mixer_width    max layer mixer line width support.
314  * @max_mixer_blendstages max layer mixer blend stages or
315  *                       supported z order
316  * @qseed_type         qseed2 or qseed3 support.
317  * @smart_dma_rev      Supported version of SmartDMA feature.
318  * @ubwc_version       UBWC feature version (0x0 for not supported)
319  * @has_src_split      source split feature status
320  * @has_dim_layer      dim layer feature status
321  * @has_idle_pc        indicate if idle power collapse feature is supported
322  * @has_3d_merge       indicate if 3D merge is supported
323  * @max_linewidth      max linewidth for sspp
324  * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
325  * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
326  * @max_vdeci_exp      max vertical decimation supported (max is 2^value)
327  */
328 struct dpu_caps {
329 	u32 max_mixer_width;
330 	u32 max_mixer_blendstages;
331 	u32 qseed_type;
332 	u32 smart_dma_rev;
333 	u32 ubwc_version;
334 	bool has_src_split;
335 	bool has_dim_layer;
336 	bool has_idle_pc;
337 	bool has_3d_merge;
338 	/* SSPP limits */
339 	u32 max_linewidth;
340 	u32 pixel_ram_size;
341 	u32 max_hdeci_exp;
342 	u32 max_vdeci_exp;
343 };
344 
345 /**
346  * struct dpu_sspp_sub_blks : SSPP sub-blocks
347  * common: Pointer to common configurations shared by sub blocks
348  * @creq_vblank: creq priority during vertical blanking
349  * @danger_vblank: danger priority during vertical blanking
350  * @maxdwnscale: max downscale ratio supported(without DECIMATION)
351  * @maxupscale:  maxupscale ratio supported
352  * @smart_dma_priority: hw priority of rect1 of multirect pipe
353  * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
354  * @qseed_ver: qseed version
355  * @src_blk:
356  * @scaler_blk:
357  * @csc_blk:
358  * @hsic:
359  * @memcolor:
360  * @pcc_blk:
361  * @igc_blk:
362  * @format_list: Pointer to list of supported formats
363  * @num_formats: Number of supported formats
364  * @virt_format_list: Pointer to list of supported formats for virtual planes
365  * @virt_num_formats: Number of supported formats for virtual planes
366  */
367 struct dpu_sspp_sub_blks {
368 	u32 creq_vblank;
369 	u32 danger_vblank;
370 	u32 maxdwnscale;
371 	u32 maxupscale;
372 	u32 smart_dma_priority;
373 	u32 max_per_pipe_bw;
374 	u32 qseed_ver;
375 	struct dpu_src_blk src_blk;
376 	struct dpu_scaler_blk scaler_blk;
377 	struct dpu_pp_blk csc_blk;
378 	struct dpu_pp_blk hsic_blk;
379 	struct dpu_pp_blk memcolor_blk;
380 	struct dpu_pp_blk pcc_blk;
381 	struct dpu_pp_blk igc_blk;
382 
383 	const u32 *format_list;
384 	u32 num_formats;
385 	const u32 *virt_format_list;
386 	u32 virt_num_formats;
387 };
388 
389 /**
390  * struct dpu_lm_sub_blks:      information of mixer block
391  * @maxwidth:               Max pixel width supported by this mixer
392  * @maxblendstages:         Max number of blend-stages supported
393  * @blendstage_base:        Blend-stage register base offset
394  * @gc: gamma correction block
395  */
396 struct dpu_lm_sub_blks {
397 	u32 maxwidth;
398 	u32 maxblendstages;
399 	u32 blendstage_base[MAX_BLOCKS];
400 	struct dpu_pp_blk gc;
401 };
402 
403 /**
404  * struct dpu_dspp_sub_blks: Information of DSPP block
405  * @gc : gamma correction block
406  * @pcc: pixel color correction block
407  */
408 struct dpu_dspp_sub_blks {
409 	struct dpu_pp_blk gc;
410 	struct dpu_pp_blk pcc;
411 };
412 
413 struct dpu_pingpong_sub_blks {
414 	struct dpu_pp_blk te;
415 	struct dpu_pp_blk te2;
416 	struct dpu_pp_blk dither;
417 };
418 
419 /**
420  * dpu_clk_ctrl_type - Defines top level clock control signals
421  */
422 enum dpu_clk_ctrl_type {
423 	DPU_CLK_CTRL_NONE,
424 	DPU_CLK_CTRL_VIG0,
425 	DPU_CLK_CTRL_VIG1,
426 	DPU_CLK_CTRL_VIG2,
427 	DPU_CLK_CTRL_VIG3,
428 	DPU_CLK_CTRL_VIG4,
429 	DPU_CLK_CTRL_RGB0,
430 	DPU_CLK_CTRL_RGB1,
431 	DPU_CLK_CTRL_RGB2,
432 	DPU_CLK_CTRL_RGB3,
433 	DPU_CLK_CTRL_DMA0,
434 	DPU_CLK_CTRL_DMA1,
435 	DPU_CLK_CTRL_CURSOR0,
436 	DPU_CLK_CTRL_CURSOR1,
437 	DPU_CLK_CTRL_INLINE_ROT0_SSPP,
438 	DPU_CLK_CTRL_REG_DMA,
439 	DPU_CLK_CTRL_MAX,
440 };
441 
442 /* struct dpu_clk_ctrl_reg : Clock control register
443  * @reg_off:           register offset
444  * @bit_off:           bit offset
445  */
446 struct dpu_clk_ctrl_reg {
447 	u32 reg_off;
448 	u32 bit_off;
449 };
450 
451 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info
452  * @id:                index identifying this block
453  * @base:              register base offset to mdss
454  * @features           bit mask identifying sub-blocks/features
455  * @highest_bank_bit:  UBWC parameter
456  * @ubwc_static:       ubwc static configuration
457  * @ubwc_swizzle:      ubwc default swizzle setting
458  * @clk_ctrls          clock control register definition
459  */
460 struct dpu_mdp_cfg {
461 	DPU_HW_BLK_INFO;
462 	u32 highest_bank_bit;
463 	u32 ubwc_swizzle;
464 	struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
465 };
466 
467 /* struct dpu_ctl_cfg : MDP CTL instance info
468  * @id:                index identifying this block
469  * @base:              register base offset to mdss
470  * @features           bit mask identifying sub-blocks/features
471  * @intr_start:        interrupt index for CTL_START
472  */
473 struct dpu_ctl_cfg {
474 	DPU_HW_BLK_INFO;
475 	s32 intr_start;
476 };
477 
478 /**
479  * struct dpu_sspp_cfg - information of source pipes
480  * @id:                index identifying this block
481  * @base               register offset of this block
482  * @features           bit mask identifying sub-blocks/features
483  * @sblk:              SSPP sub-blocks information
484  * @xin_id:            bus client identifier
485  * @clk_ctrl           clock control identifier
486  * @type               sspp type identifier
487  */
488 struct dpu_sspp_cfg {
489 	DPU_HW_BLK_INFO;
490 	const struct dpu_sspp_sub_blks *sblk;
491 	u32 xin_id;
492 	enum dpu_clk_ctrl_type clk_ctrl;
493 	u32 type;
494 };
495 
496 /**
497  * struct dpu_lm_cfg - information of layer mixer blocks
498  * @id:                index identifying this block
499  * @base               register offset of this block
500  * @features           bit mask identifying sub-blocks/features
501  * @sblk:              LM Sub-blocks information
502  * @pingpong:          ID of connected PingPong, PINGPONG_MAX if unsupported
503  * @lm_pair_mask:      Bitmask of LMs that can be controlled by same CTL
504  */
505 struct dpu_lm_cfg {
506 	DPU_HW_BLK_INFO;
507 	const struct dpu_lm_sub_blks *sblk;
508 	u32 pingpong;
509 	u32 dspp;
510 	unsigned long lm_pair_mask;
511 };
512 
513 /**
514  * struct dpu_dspp_cfg - information of DSPP blocks
515  * @id                 enum identifying this block
516  * @base               register offset of this block
517  * @features           bit mask identifying sub-blocks/features
518  *                     supported by this block
519  * @sblk               sub-blocks information
520  */
521 struct dpu_dspp_cfg  {
522 	DPU_HW_BLK_INFO;
523 	const struct dpu_dspp_sub_blks *sblk;
524 };
525 
526 /**
527  * struct dpu_pingpong_cfg - information of PING-PONG blocks
528  * @id                 enum identifying this block
529  * @base               register offset of this block
530  * @features           bit mask identifying sub-blocks/features
531  * @intr_done:         index for PINGPONG done interrupt
532  * @intr_rdptr:        index for PINGPONG readpointer done interrupt
533  * @sblk               sub-blocks information
534  */
535 struct dpu_pingpong_cfg  {
536 	DPU_HW_BLK_INFO;
537 	u32 merge_3d;
538 	s32 intr_done;
539 	s32 intr_rdptr;
540 	const struct dpu_pingpong_sub_blks *sblk;
541 };
542 
543 /**
544  * struct dpu_merge_3d_cfg - information of DSPP blocks
545  * @id                 enum identifying this block
546  * @base               register offset of this block
547  * @features           bit mask identifying sub-blocks/features
548  *                     supported by this block
549  * @sblk               sub-blocks information
550  */
551 struct dpu_merge_3d_cfg  {
552 	DPU_HW_BLK_INFO;
553 	const struct dpu_merge_3d_sub_blks *sblk;
554 };
555 
556 /**
557  * struct dpu_intf_cfg - information of timing engine blocks
558  * @id                 enum identifying this block
559  * @base               register offset of this block
560  * @features           bit mask identifying sub-blocks/features
561  * @type:              Interface type(DSI, DP, HDMI)
562  * @controller_id:     Controller Instance ID in case of multiple of intf type
563  * @prog_fetch_lines_worst_case	Worst case latency num lines needed to prefetch
564  * @intr_underrun:	index for INTF underrun interrupt
565  * @intr_vsync:	        index for INTF VSYNC interrupt
566  */
567 struct dpu_intf_cfg  {
568 	DPU_HW_BLK_INFO;
569 	u32 type;   /* interface type*/
570 	u32 controller_id;
571 	u32 prog_fetch_lines_worst_case;
572 	s32 intr_underrun;
573 	s32 intr_vsync;
574 };
575 
576 /**
577  * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
578  * @pps                pixel per seconds
579  * @ot_limit           OT limit to use up to specified pixel per second
580  */
581 struct dpu_vbif_dynamic_ot_cfg {
582 	u64 pps;
583 	u32 ot_limit;
584 };
585 
586 /**
587  * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table
588  * @count              length of cfg
589  * @cfg                pointer to array of configuration settings with
590  *                     ascending requirements
591  */
592 struct dpu_vbif_dynamic_ot_tbl {
593 	u32 count;
594 	const struct dpu_vbif_dynamic_ot_cfg *cfg;
595 };
596 
597 /**
598  * struct dpu_vbif_qos_tbl - QoS priority table
599  * @npriority_lvl      num of priority level
600  * @priority_lvl       pointer to array of priority level in ascending order
601  */
602 struct dpu_vbif_qos_tbl {
603 	u32 npriority_lvl;
604 	const u32 *priority_lvl;
605 };
606 
607 /**
608  * struct dpu_vbif_cfg - information of VBIF blocks
609  * @id                 enum identifying this block
610  * @base               register offset of this block
611  * @features           bit mask identifying sub-blocks/features
612  * @ot_rd_limit        default OT read limit
613  * @ot_wr_limit        default OT write limit
614  * @xin_halt_timeout   maximum time (in usec) for xin to halt
615  * @dynamic_ot_rd_tbl  dynamic OT read configuration table
616  * @dynamic_ot_wr_tbl  dynamic OT write configuration table
617  * @qos_rt_tbl         real-time QoS priority table
618  * @qos_nrt_tbl        non-real-time QoS priority table
619  * @memtype_count      number of defined memtypes
620  * @memtype            array of xin memtype definitions
621  */
622 struct dpu_vbif_cfg {
623 	DPU_HW_BLK_INFO;
624 	u32 default_ot_rd_limit;
625 	u32 default_ot_wr_limit;
626 	u32 xin_halt_timeout;
627 	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
628 	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
629 	struct dpu_vbif_qos_tbl qos_rt_tbl;
630 	struct dpu_vbif_qos_tbl qos_nrt_tbl;
631 	u32 memtype_count;
632 	u32 memtype[MAX_XIN_COUNT];
633 };
634 /**
635  * struct dpu_reg_dma_cfg - information of lut dma blocks
636  * @id                 enum identifying this block
637  * @base               register offset of this block
638  * @features           bit mask identifying sub-blocks/features
639  * @version            version of lutdma hw block
640  * @trigger_sel_off    offset to trigger select registers of lutdma
641  */
642 struct dpu_reg_dma_cfg {
643 	DPU_HW_BLK_INFO;
644 	u32 version;
645 	u32 trigger_sel_off;
646 	u32 xin_id;
647 	enum dpu_clk_ctrl_type clk_ctrl;
648 };
649 
650 /**
651  * Define CDP use cases
652  * @DPU_PERF_CDP_UDAGE_RT: real-time use cases
653  * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD
654  */
655 enum {
656 	DPU_PERF_CDP_USAGE_RT,
657 	DPU_PERF_CDP_USAGE_NRT,
658 	DPU_PERF_CDP_USAGE_MAX
659 };
660 
661 /**
662  * struct dpu_perf_cdp_cfg - define CDP use case configuration
663  * @rd_enable: true if read pipe CDP is enabled
664  * @wr_enable: true if write pipe CDP is enabled
665  */
666 struct dpu_perf_cdp_cfg {
667 	bool rd_enable;
668 	bool wr_enable;
669 };
670 
671 /**
672  * struct dpu_perf_cfg - performance control settings
673  * @max_bw_low         low threshold of maximum bandwidth (kbps)
674  * @max_bw_high        high threshold of maximum bandwidth (kbps)
675  * @min_core_ib        minimum bandwidth for core (kbps)
676  * @min_core_ib        minimum mnoc ib vote in kbps
677  * @min_llcc_ib        minimum llcc ib vote in kbps
678  * @min_dram_ib        minimum dram ib vote in kbps
679  * @core_ib_ff         core instantaneous bandwidth fudge factor
680  * @core_clk_ff        core clock fudge factor
681  * @comp_ratio_rt      string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
682  * @comp_ratio_nrt     string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
683  * @undersized_prefill_lines   undersized prefill in lines
684  * @xtra_prefill_lines         extra prefill latency in lines
685  * @dest_scale_prefill_lines   destination scaler latency in lines
686  * @macrotile_perfill_lines    macrotile latency in lines
687  * @yuv_nv12_prefill_lines     yuv_nv12 latency in lines
688  * @linear_prefill_lines       linear latency in lines
689  * @downscaling_prefill_lines  downscaling latency in lines
690  * @amortizable_theshold minimum y position for traffic shaping prefill
691  * @min_prefill_lines  minimum pipeline latency in lines
692  * @clk_inefficiency_factor DPU src clock inefficiency factor
693  * @bw_inefficiency_factor DPU axi bus bw inefficiency factor
694  * @safe_lut_tbl: LUT tables for safe signals
695  * @danger_lut_tbl: LUT tables for danger signals
696  * @qos_lut_tbl: LUT tables for QoS signals
697  * @cdp_cfg            cdp use case configurations
698  */
699 struct dpu_perf_cfg {
700 	u32 max_bw_low;
701 	u32 max_bw_high;
702 	u32 min_core_ib;
703 	u32 min_llcc_ib;
704 	u32 min_dram_ib;
705 	const char *core_ib_ff;
706 	const char *core_clk_ff;
707 	const char *comp_ratio_rt;
708 	const char *comp_ratio_nrt;
709 	u32 undersized_prefill_lines;
710 	u32 xtra_prefill_lines;
711 	u32 dest_scale_prefill_lines;
712 	u32 macrotile_prefill_lines;
713 	u32 yuv_nv12_prefill_lines;
714 	u32 linear_prefill_lines;
715 	u32 downscaling_prefill_lines;
716 	u32 amortizable_threshold;
717 	u32 min_prefill_lines;
718 	u32 clk_inefficiency_factor;
719 	u32 bw_inefficiency_factor;
720 	u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
721 	u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
722 	struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
723 	struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX];
724 };
725 
726 /**
727  * struct dpu_mdss_cfg - information of MDSS HW
728  * This is the main catalog data structure representing
729  * this HW version. Contains number of instances,
730  * register offsets, capabilities of the all MDSS HW sub-blocks.
731  *
732  * @dma_formats        Supported formats for dma pipe
733  * @cursor_formats     Supported formats for cursor pipe
734  * @vig_formats        Supported formats for vig pipe
735  * @mdss_irqs:         Bitmap with the irqs supported by the target
736  */
737 struct dpu_mdss_cfg {
738 	u32 hwversion;
739 
740 	const struct dpu_caps *caps;
741 
742 	u32 mdp_count;
743 	const struct dpu_mdp_cfg *mdp;
744 
745 	u32 ctl_count;
746 	const struct dpu_ctl_cfg *ctl;
747 
748 	u32 sspp_count;
749 	const struct dpu_sspp_cfg *sspp;
750 
751 	u32 mixer_count;
752 	const struct dpu_lm_cfg *mixer;
753 
754 	u32 pingpong_count;
755 	const struct dpu_pingpong_cfg *pingpong;
756 
757 	u32 merge_3d_count;
758 	const struct dpu_merge_3d_cfg *merge_3d;
759 
760 	u32 intf_count;
761 	const struct dpu_intf_cfg *intf;
762 
763 	u32 vbif_count;
764 	const struct dpu_vbif_cfg *vbif;
765 
766 	u32 reg_dma_count;
767 	struct dpu_reg_dma_cfg dma_cfg;
768 
769 	u32 ad_count;
770 
771 	u32 dspp_count;
772 	const struct dpu_dspp_cfg *dspp;
773 
774 	/* Add additional block data structures here */
775 
776 	struct dpu_perf_cfg perf;
777 	const struct dpu_format_extended *dma_formats;
778 	const struct dpu_format_extended *cursor_formats;
779 	const struct dpu_format_extended *vig_formats;
780 
781 	unsigned long mdss_irqs;
782 };
783 
784 struct dpu_mdss_hw_cfg_handler {
785 	u32 hw_rev;
786 	void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg);
787 };
788 
789 /*
790  * Access Macros
791  */
792 #define BLK_MDP(s) ((s)->mdp)
793 #define BLK_CTL(s) ((s)->ctl)
794 #define BLK_VIG(s) ((s)->vig)
795 #define BLK_RGB(s) ((s)->rgb)
796 #define BLK_DMA(s) ((s)->dma)
797 #define BLK_CURSOR(s) ((s)->cursor)
798 #define BLK_MIXER(s) ((s)->mixer)
799 #define BLK_PINGPONG(s) ((s)->pingpong)
800 #define BLK_INTF(s) ((s)->intf)
801 #define BLK_AD(s) ((s)->ad)
802 #define BLK_DSPP(s) ((s)->dspp)
803 #define BLK_MERGE3d(s) ((s)->merge_3d)
804 
805 /**
806  * dpu_hw_catalog_init - dpu hardware catalog init API retrieves
807  * hardcoded target specific catalog information in config structure
808  * @hw_rev:       caller needs provide the hardware revision.
809  *
810  * Return: dpu config structure
811  */
812 struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev);
813 
814 /**
815  * dpu_hw_catalog_deinit - dpu hardware catalog cleanup
816  * @dpu_cfg:      pointer returned from init function
817  */
818 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg);
819 
820 #endif /* _DPU_HW_CATALOG_H */
821