Searched refs:DPLL_SYNCLOCK_ENABLE (Results 1 – 5 of 5) sorted by relevance
333 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { in cdv_restore_display_registers()334 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()339 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { in cdv_restore_display_registers()340 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
226 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()670 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()716 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
231 #define DPLL_SYNCLOCK_ENABLE (1 << 29) macro
151 #define DPLL_SYNCLOCK_ENABLE (1 << 29) macro
3485 #define DPLL_SYNCLOCK_ENABLE (1 << 29) macro
