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Searched refs:DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h5675 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000ffffL macro
Ddce_8_0_sh_mask.h7751 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff macro
Ddce_11_0_sh_mask.h6689 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff macro
Ddce_10_0_sh_mask.h6795 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff macro
Ddce_11_2_sh_mask.h7769 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff macro
Ddce_12_0_sh_mask.h4707 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h1385 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … macro
Ddcn_2_1_0_sh_mask.h2183 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … macro
Ddcn_3_0_1_sh_mask.h2328 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … macro
Ddcn_1_0_sh_mask.h3677 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … macro
Ddcn_3_1_2_sh_mask.h1800 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … macro
Ddcn_3_0_2_sh_mask.h2254 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … macro
Ddcn_2_0_0_sh_mask.h2451 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … macro
Ddcn_3_0_0_sh_mask.h2320 #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … macro