Home
last modified time | relevance | path

Searched refs:DISPCLK_FREQ_CHANGE_CNTL (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dccg.h40 SR(DISPCLK_FREQ_CHANGE_CNTL)
73 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
74 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
75 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
76 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
77 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
78 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
79 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
80 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
131 type DISPCLK_FREQ_CHANGE_CNTL;\
[all …]
Ddcn20_dccg.c104 REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, in dccg2_set_fifo_errdet_ovr_en()
Ddcn20_hwseq.c247 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); in dcn20_dccg_init()
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce/
Ddce_hwseq.h235 SR(DISPCLK_FREQ_CHANGE_CNTL), \
299 SR(DISPCLK_FREQ_CHANGE_CNTL), \
347 SR(DISPCLK_FREQ_CHANGE_CNTL), \
380 SR(DISPCLK_FREQ_CHANGE_CNTL), \
432 SR(DISPCLK_FREQ_CHANGE_CNTL), \
489 SR(DISPCLK_FREQ_CHANGE_CNTL), \
601 uint32_t DISPCLK_FREQ_CHANGE_CNTL; member
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c764 SR(DISPCLK_FREQ_CHANGE_CNTL), \