| /Linux-v5.15/Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.txt | 45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
95 - reg : the DDR PHY register range and length
104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
115 - reg : the DDR sequencer register range and length
136 - reg : the DDR Arbiter register range and length
|
| /Linux-v5.15/Documentation/ABI/testing/ |
| D | sysfs-driver-bd9571mwv-regulator | 5 Description: Read/write the current state of DDR Backup Mode, which controls
6 if DDR power rails will be kept powered during system suspend.
10 A. With a momentary power switch (or pulse signal), DDR
26 DDR Backup Mode must be explicitly enabled by the user,
|
| /Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | ddr.txt | 1 Freescale DDR memory controller
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
|
| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
|
| D | brcm,bcm2835-cprman.txt | 27 - DSI0 DDR clock
30 - DSI1 DDR clock
|
| D | armada3700-periph-clock.txt | 26 11 ddr_phy DDR PHY
27 12 ddr_fclk DDR F clock
|
| /Linux-v5.15/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
179 Control registers for this memory controller's DDR SHIMPHY.
183 - reg : the DDR SHIMPHY register range
185 == MEMC DDR control
198 - reg : the MEMC DDR register range
|
| /Linux-v5.15/drivers/gpio/ |
| D | gpio-mb86s7x.c | 31 #define DDR(x) (0x10 + x / 8 * 4) macro
83 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
85 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
108 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
110 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
|
| /Linux-v5.15/drivers/memory/ |
| D | Kconfig | 11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
17 config DDR config
20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
41 Starting with the at91sam9g45, this controller supports SDR, DDR and
42 LP-DDR memories.
63 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
95 select DDR
|
| /Linux-v5.15/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 5 - devfreq-events: Node to get DDR loading, Refer to
21 It should be a DCF interrupt. When DDR DVFS finishes
26 Following properties relate to DDR timing:
65 When DDR frequency is less than DRAM_DLL_DISB_FREQ,
70 MHz (Mega Hz). When DDR frequency is less than
76 when the DDR frequency is less then ddr3_odt_dis_freq,
102 When DDR frequency is less then ddr3_odt_dis_freq,
128 MHz (Mega Hz). When the DDR frequency is less then
|
| /Linux-v5.15/drivers/mtd/lpddr/ |
| D | Kconfig | 10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
|
| /Linux-v5.15/Documentation/devicetree/bindings/ddr/ |
| D | lpddr3-timings.txt | 7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
|
| D | lpddr2-timings.txt | 5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
|
| /Linux-v5.15/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
75 movs r0, r0 @ see if DDR or SDR
|
| /Linux-v5.15/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx7ulp-pinctrl.txt | 4 ports and IOMUXC DDR for DDR interface.
|
| /Linux-v5.15/Documentation/driver-api/memory-devices/ |
| D | ti-emif.rst | 38 DDR device details and other board dependent and SoC dependent
41 - DDR device details: 'struct ddr_device_info'
|
| /Linux-v5.15/Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
70 counting the number of bytes (as opposed to the number of bursts) from DDR
|
| D | hisi-pmu.rst | 81 5'b01110: comes from the local DDR;
82 5'b01111: comes from the cross-die DDR;
83 5'b10000: comes from cross-socket DDR;
|
| /Linux-v5.15/Documentation/devicetree/bindings/mfd/ |
| D | bd9571mwv.txt | 28 - rohm,ddr-backup-power : Value to use for DDR-Backup Power (default 0).
29 This is a bitmask that specifies which DDR power
|
| /Linux-v5.15/Documentation/devicetree/bindings/mips/img/ |
| D | xilfpga.txt | 20 - 128Mbyte DDR RAM at 0x0000_0000
74 DDR initialization is already handled by a HW IP block.
|
| /Linux-v5.15/drivers/perf/hisilicon/ |
| D | Kconfig | 7 Agent performance monitor and DDR Controller performance monitor.
|
| /Linux-v5.15/Documentation/arm/samsung-s3c24xx/ |
| D | s3c2413.rst | 9 interface and mobile DDR memory support. See the S3C2412 support
|
| /Linux-v5.15/arch/arm64/boot/dts/intel/ |
| D | keembay-evm.dts | 29 /* 2GB of DDR memory. */
|
| /Linux-v5.15/arch/mips/include/asm/mach-loongson2ef/ |
| D | loongson.h | 312 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
314 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
|
| /Linux-v5.15/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra30.c | 2203 …PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, …
2204 …PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, …
2205 …PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, …
2262 …PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, …
2263 …PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, …
2264 …PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, …
2265 …PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, …
2266 …PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, …
2267 …PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, …
2268 …PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, …
[all …]
|
