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Searched refs:DDI_BUF_CTL (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Ddisplay.c215 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= in emulate_monitor_status_change()
218 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
278 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= in emulate_monitor_status_change()
280 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= in emulate_monitor_status_change()
307 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
309 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
337 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= in emulate_monitor_status_change()
339 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= in emulate_monitor_status_change()
418 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
419 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
[all …]
Dhandlers.c800 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
819 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); in fdi_auto_training_started()
2773 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2774 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2775 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2776 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2777 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_fdi.c615 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
617 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
661 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
663 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); in hsw_fdi_link_train()
664 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
Dintel_ddi.c166 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_idle()
183 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_active()
715 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_get_encoder_pipes()
1444 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in hsw_set_signal_levels()
1445 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
2744 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_disable_ddi_buf()
2747 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); in intel_disable_ddi_buf()
3117 intel_de_write(dev_priv, DDI_BUF_CTL(port), in intel_enable_ddi_hdmi()
3319 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_prepare_link_retrain()
3321 intel_de_write(dev_priv, DDI_BUF_CTL(port), in intel_ddi_prepare_link_retrain()
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Dintel_tc.c358 val = intel_uncore_read(uncore, DDI_BUF_CTL(port)); in adl_tc_phy_take_ownership()
363 intel_uncore_write(uncore, DDI_BUF_CTL(port), val); in adl_tc_phy_take_ownership()
403 val = intel_uncore_read(uncore, DDI_BUF_CTL(port)); in adl_tc_phy_is_owned()
Dicl_dsi.c558 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in gen11_dsi_enable_ddi_buffer()
560 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); in gen11_dsi_enable_ddi_buffer()
562 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in gen11_dsi_enable_ddi_buffer()
1393 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in gen11_dsi_disable_port()
1395 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); in gen11_dsi_disable_port()
1397 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in gen11_dsi_disable_port()
Dintel_display.c11463 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) in intel_ddi_crt_present()
11547 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; in intel_setup_outputs()
/Linux-v5.15/drivers/gpu/drm/i915/
Di915_reg.h10249 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) macro