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Searched refs:CP_INT_CNTL_RING0 (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c2706 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2707 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2708 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2710 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
5712 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_gfx_eop_interrupt_state()
5782 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_reg_fault_state()
5801 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_inst_fault_state()
5827 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
5836 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
Dgfx_v8_0.c3899 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3900 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3901 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3902 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
6450 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()
6510 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, in gfx_v8_0_set_priv_reg_fault_state()
6521 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE, in gfx_v8_0_set_priv_inst_fault_state()
6587 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag); in gfx_v8_0_set_cp_ecc_int_state()
Dgfx_v10_0.c5312 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
5314 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
5316 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
5318 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
9034 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9040 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9187 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_reg_fault_state()
9206 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_inst_fault_state()
Dsid.h1304 #define CP_INT_CNTL_RING0 0x306A macro
/Linux-v5.15/drivers/gpu/drm/radeon/
Dsi.c5143 u32 tmp = RREG32(CP_INT_CNTL_RING0); in si_enable_gui_idle_interrupt()
5151 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5948 tmp = RREG32(CP_INT_CNTL_RING0) & in si_disable_interrupt_state()
5950 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
6066 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6098 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
Dsid.h1276 #define CP_INT_CNTL_RING0 0xC1A8 macro
Dcik.c5760 u32 tmp = RREG32(CP_INT_CNTL_RING0); in cik_enable_gui_idle_interrupt()
5766 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
6859 tmp = RREG32(CP_INT_CNTL_RING0) & in cik_disable_interrupt_state()
6861 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
Dcikd.h1331 #define CP_INT_CNTL_RING0 0xC1A8 macro