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Searched refs:CP_HQD_PQ_CONTROL (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dmes_v10_1.c662 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in mes_v10_1_mqd_init()
664 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in mes_v10_1_mqd_init()
667 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in mes_v10_1_mqd_init()
669 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in mes_v10_1_mqd_init()
670 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in mes_v10_1_mqd_init()
671 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v10_1_mqd_init()
672 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in mes_v10_1_mqd_init()
Damdgpu_amdkfd_gfx_v10.c269 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in kgd_hqd_load()
Damdgpu_amdkfd_gfx_v9.c283 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in kgd_gfx_v9_hqd_load()
Damdgpu_amdkfd_gfx_v10_3.c254 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in hqd_load_v10_3()
Dgfx_v8_0.c4506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v8_0_mqd_init()
4508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v8_0_mqd_init()
4511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v8_0_mqd_init()
4513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v8_0_mqd_init()
4514 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v8_0_mqd_init()
4515 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v8_0_mqd_init()
4516 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v8_0_mqd_init()
Dgfx_v9_0.c3543 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v9_0_mqd_init()
3545 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v9_0_mqd_init()
3548 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v9_0_mqd_init()
3550 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v9_0_mqd_init()
3551 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v9_0_mqd_init()
3552 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v9_0_mqd_init()
3553 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v9_0_mqd_init()
Dgfx_v10_0.c6939 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v10_0_compute_mqd_init()
6941 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v10_0_compute_mqd_init()
6944 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v10_0_compute_mqd_init()
6946 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v10_0_compute_mqd_init()
6947 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in gfx_v10_0_compute_mqd_init()
6948 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v10_0_compute_mqd_init()
6949 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v10_0_compute_mqd_init()
/Linux-v5.15/drivers/gpu/drm/radeon/
Dcikd.h1519 #define CP_HQD_PQ_CONTROL 0xC958 macro
Dcik.c4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()