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Searched refs:CLKID_VCLK_DIV2 (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.15/include/dt-bindings/clock/
Daxg-clkc.h88 #define CLKID_VCLK_DIV2 123 macro
Dgxbb-clkc.h135 #define CLKID_VCLK_DIV2 186 macro
Dg12a-clkc.h114 #define CLKID_VCLK_DIV2 149 macro
/Linux-v5.15/drivers/clk/meson/
Dmeson8b.h121 #define CLKID_VCLK_DIV2 142 macro
Dmeson8b.c2848 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3054 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3271 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
Dgxbb.c2873 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
3084 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
Dg12a.c4399 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4628 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4892 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
Daxg.c2017 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,