Searched refs:CGU_CLK_GATE (Results 1 – 9 of 9) sorted by relevance
167 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,184 "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,204 "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,211 "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,218 "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,225 "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,232 "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,239 "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,246 "bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,253 "lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,[all …]
389 "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,433 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,440 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,447 "msc2", CGU_CLK_DIV | CGU_CLK_GATE,454 "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,491 "pcm", CGU_CLK_MUX | CGU_CLK_GATE,498 "gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,507 "hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,516 "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,531 "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,[all …]
207 "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,214 "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,227 "tve", CGU_CLK_GATE | CGU_CLK_MUX,233 "lpclk", CGU_CLK_GATE | CGU_CLK_MUX,239 "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,249 "pcm", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,264 "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,288 "cim", CGU_CLK_DIV | CGU_CLK_GATE,297 "ssi0", CGU_CLK_GATE,302 "ssi1", CGU_CLK_GATE,[all …]
227 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,259 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,266 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,274 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,283 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,299 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,306 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,339 "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,348 "emc", CGU_CLK_GATE,354 "efuse", CGU_CLK_GATE,[all …]
125 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,135 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,142 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,150 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,173 "uart", CGU_CLK_GATE,179 "dma", CGU_CLK_GATE,185 "adc", CGU_CLK_GATE,191 "i2c", CGU_CLK_GATE,197 "aic", CGU_CLK_GATE,203 "mmc0", CGU_CLK_GATE,[all …]
140 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,156 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,164 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,172 "mmc", CGU_CLK_DIV | CGU_CLK_GATE,179 "uhc", CGU_CLK_DIV | CGU_CLK_GATE,186 "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,196 "uart0", CGU_CLK_GATE,202 "uart1", CGU_CLK_GATE,208 "dma", CGU_CLK_GATE,214 "ipu", CGU_CLK_GATE,[all …]
253 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,285 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,292 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,300 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,308 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,322 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,329 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,336 "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,370 "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,379 "emc", CGU_CLK_GATE,[all …]
156 CGU_CLK_GATE = BIT(2), enumerator
559 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_enable()579 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_disable()594 if (clk_info->type & CGU_CLK_GATE) in ingenic_clk_is_enabled()727 caps &= ~(CGU_CLK_GATE | CGU_CLK_FIXDIV); in ingenic_register_clock()
