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Searched refs:BIT_ULL (Results 1 – 25 of 355) sorted by relevance

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/Linux-v5.15/drivers/gpu/drm/panfrost/
Dpanfrost_features.h45 BIT_ULL(HW_FEATURE_LD_ST_LEA_TEX) | \
46 BIT_ULL(HW_FEATURE_LINEAR_FILTER_FLOAT) | \
47 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
48 BIT_ULL(HW_FEATURE_V4))
51 BIT_ULL(HW_FEATURE_LD_ST_LEA_TEX) | \
52 BIT_ULL(HW_FEATURE_LINEAR_FILTER_FLOAT) | \
53 BIT_ULL(HW_FEATURE_ATTR_AUTO_TYPE_INFERRAL) | \
54 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
55 BIT_ULL(HW_FEATURE_V4))
58 BIT_ULL(HW_FEATURE_32_BIT_UNIFORM_ADDRESS) | \
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Dpanfrost_issues.h132 BIT_ULL(HW_ISSUE_9435))
135 BIT_ULL(HW_ISSUE_6367) | \
136 BIT_ULL(HW_ISSUE_6787) | \
137 BIT_ULL(HW_ISSUE_8408) | \
138 BIT_ULL(HW_ISSUE_9510) | \
139 BIT_ULL(HW_ISSUE_10649) | \
140 BIT_ULL(HW_ISSUE_10676) | \
141 BIT_ULL(HW_ISSUE_10883) | \
142 BIT_ULL(HW_ISSUE_11020) | \
143 BIT_ULL(HW_ISSUE_11035) | \
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/Linux-v5.15/drivers/mmc/host/
Dcavium.h120 #define MIO_EMM_DMA_FIFO_CFG_CLR BIT_ULL(16)
124 #define MIO_EMM_DMA_FIFO_CMD_RW BIT_ULL(62)
125 #define MIO_EMM_DMA_FIFO_CMD_INTDIS BIT_ULL(60)
126 #define MIO_EMM_DMA_FIFO_CMD_SWAP32 BIT_ULL(59)
127 #define MIO_EMM_DMA_FIFO_CMD_SWAP16 BIT_ULL(58)
128 #define MIO_EMM_DMA_FIFO_CMD_SWAP8 BIT_ULL(57)
129 #define MIO_EMM_DMA_FIFO_CMD_ENDIAN BIT_ULL(56)
132 #define MIO_EMM_CMD_SKIP_BUSY BIT_ULL(62)
134 #define MIO_EMM_CMD_VAL BIT_ULL(59)
135 #define MIO_EMM_CMD_DBUF BIT_ULL(55)
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/Linux-v5.15/drivers/net/ethernet/cavium/thunder/
Dthunder_bgx.h36 #define CMR_PKT_TX_EN BIT_ULL(13)
37 #define CMR_PKT_RX_EN BIT_ULL(14)
38 #define CMR_EN BIT_ULL(15)
40 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
57 #define RX_DMACX_CAM_EN BIT_ULL(48)
87 #define SPU_CTL_LOW_POWER BIT_ULL(11)
88 #define SPU_CTL_LOOPBACK BIT_ULL(14)
89 #define SPU_CTL_RESET BIT_ULL(15)
91 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)
93 #define SPU_STATUS2_RCVFLT BIT_ULL(10)
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/Linux-v5.15/arch/mips/include/asm/
Dcpu.h366 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
367 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
368 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
369 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
370 #define MIPS_CPU_TX39_CACHE BIT_ULL( 4) /* TX3900-style caches */
371 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
372 #define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
373 #define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
374 #define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
375 #define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
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/Linux-v5.15/drivers/iommu/intel/
Dcap_audit.h13 #define CAP_FL5LP_MASK BIT_ULL(60)
14 #define CAP_PI_MASK BIT_ULL(59)
15 #define CAP_FL1GP_MASK BIT_ULL(56)
16 #define CAP_RD_MASK BIT_ULL(55)
17 #define CAP_WD_MASK BIT_ULL(54)
20 #define CAP_PSI_MASK BIT_ULL(39)
23 #define CAP_ZLR_MASK BIT_ULL(22)
26 #define CAP_CM_MASK BIT_ULL(7)
27 #define CAP_PHMR_MASK BIT_ULL(6)
28 #define CAP_PLMR_MASK BIT_ULL(5)
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/Linux-v5.15/drivers/infiniband/hw/irdma/
Ddefs.h381 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
384 #define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
385 #define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)
387 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
388 #define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)
389 #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)
390 #define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)
394 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
397 #define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)
398 #define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)
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Duda_d.h17 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
18 #define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57)
22 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
23 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
24 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
39 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45)
44 #define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)
45 #define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5)
46 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
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/Linux-v5.15/drivers/gpu/drm/arm/display/komeda/
Dkomeda_dev.h16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
23 #define KOMEDA_EVENT_FULL BIT_ULL(7)
24 #define KOMEDA_EVENT_EMPTY BIT_ULL(8)
26 #define KOMEDA_ERR_TETO BIT_ULL(14)
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/Linux-v5.15/arch/x86/include/asm/
Dmce.h13 #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
14 #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
15 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
19 #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
20 #define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */
21 #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
24 #define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */
25 #define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */
26 #define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */
27 #define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */
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/Linux-v5.15/drivers/net/ethernet/intel/ice/
Dice_flow.h12 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
13 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
15 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
16 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
18 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
19 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
21 (BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
22 BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
24 (BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
25 BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
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Dice_adminq_cmd.h902 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
903 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
904 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
905 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
906 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
907 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
908 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
909 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
910 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
911 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
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/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_display_power.c223 for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) { in __intel_display_power_is_enabled()
2053 power_domains->async_put_domains[0] &= ~BIT_ULL(domain); in async_put_domains_clear_domain()
2054 power_domains->async_put_domains[1] &= ~BIT_ULL(domain); in async_put_domains_clear_domain()
2064 if (!(async_put_domains_mask(power_domains) & BIT_ULL(domain))) in intel_display_power_grab_async_put_ref()
2093 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) in __intel_display_power_get_domain()
2181 async_put_domains_mask(power_domains) & BIT_ULL(domain), in __intel_display_power_put_domain()
2187 for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) in __intel_display_power_put_domain()
2321 power_domains->async_put_domains[1] |= BIT_ULL(domain); in __intel_display_power_put_async()
2323 power_domains->async_put_domains[0] |= BIT_ULL(domain); in __intel_display_power_put_async()
2442 drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain)); in intel_display_power_get_in_set()
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/Linux-v5.15/drivers/firmware/efi/
Dcper-x86.c11 #define VALID_LAPIC_ID BIT_ULL(0)
12 #define VALID_CPUID_INFO BIT_ULL(1)
29 #define INFO_VALID_CHECK_INFO BIT_ULL(0)
30 #define INFO_VALID_TARGET_ID BIT_ULL(1)
31 #define INFO_VALID_REQUESTOR_ID BIT_ULL(2)
32 #define INFO_VALID_RESPONDER_ID BIT_ULL(3)
33 #define INFO_VALID_IP BIT_ULL(4)
35 #define CHECK_VALID_TRANS_TYPE BIT_ULL(0)
36 #define CHECK_VALID_OPERATION BIT_ULL(1)
37 #define CHECK_VALID_LEVEL BIT_ULL(2)
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/Linux-v5.15/include/media/
Drc-map.h15 #define RC_PROTO_BIT_UNKNOWN BIT_ULL(RC_PROTO_UNKNOWN)
16 #define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER)
17 #define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5)
18 #define RC_PROTO_BIT_RC5X_20 BIT_ULL(RC_PROTO_RC5X_20)
19 #define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ)
20 #define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC)
21 #define RC_PROTO_BIT_SONY12 BIT_ULL(RC_PROTO_SONY12)
22 #define RC_PROTO_BIT_SONY15 BIT_ULL(RC_PROTO_SONY15)
23 #define RC_PROTO_BIT_SONY20 BIT_ULL(RC_PROTO_SONY20)
24 #define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC)
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/Linux-v5.15/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_regs.h367 #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)
368 #define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33)
369 #define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34)
370 #define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35)
371 #define CN6XXX_INTR_DMA0_TIME BIT_ULL(36)
372 #define CN6XXX_INTR_DMA1_TIME BIT_ULL(37)
373 #define CN6XXX_INTR_INSTR_DB_OF_ERR BIT_ULL(48)
374 #define CN6XXX_INTR_SLIST_DB_OF_ERR BIT_ULL(49)
375 #define CN6XXX_INTR_POUT_ERR BIT_ULL(50)
376 #define CN6XXX_INTR_PIN_BP_ERR BIT_ULL(51)
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Dcn23xx_pf_regs.h137 #define CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16)
186 #define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)
233 #define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62)
234 #define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48)
389 #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
425 #define CN23XX_INTR_PO_INT BIT_ULL(63)
426 #define CN23XX_INTR_PI_INT BIT_ULL(62)
427 #define CN23XX_INTR_MBOX_INT BIT_ULL(61)
428 #define CN23XX_INTR_RESEND BIT_ULL(60)
430 #define CN23XX_INTR_CINT_ENB BIT_ULL(48)
[all …]
/Linux-v5.15/drivers/extcon/
Dextcon-fsa9480.c127 [DEV_USB_OTG] = BIT_ULL(EXTCON_USB_HOST),
128 [DEV_DEDICATED_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_DCP),
129 [DEV_USB_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
130 [DEV_CAR_KIT] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP)
131 | BIT_ULL(EXTCON_JACK_LINE_OUT),
132 [DEV_UART] = BIT_ULL(EXTCON_JIG),
133 [DEV_USB] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
134 [DEV_AUDIO_2] = BIT_ULL(EXTCON_JACK_LINE_OUT),
135 [DEV_AUDIO_1] = BIT_ULL(EXTCON_JACK_LINE_OUT),
136 [DEV_AV] = BIT_ULL(EXTCON_JACK_LINE_OUT)
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/Linux-v5.15/drivers/net/ethernet/marvell/octeontx2/af/
Dcgx.h33 #define CMR_EN BIT_ULL(55)
34 #define DATA_PKT_TX_EN BIT_ULL(53)
35 #define DATA_PKT_RX_EN BIT_ULL(54)
39 #define FW_CGX_INT BIT_ULL(1)
45 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
46 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
47 #define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
48 #define CGX_DMAC_MCAST_MODE BIT_ULL(1)
49 #define CGX_DMAC_BCAST_MODE BIT_ULL(0)
51 #define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
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/Linux-v5.15/drivers/gpu/drm/i915/
Di915_gem_gtt.h36 #define PIN_NOEVICT BIT_ULL(0)
37 #define PIN_NOSEARCH BIT_ULL(1)
38 #define PIN_NONBLOCK BIT_ULL(2)
39 #define PIN_MAPPABLE BIT_ULL(3)
40 #define PIN_ZONE_4G BIT_ULL(4)
41 #define PIN_HIGH BIT_ULL(5)
42 #define PIN_OFFSET_BIAS BIT_ULL(6)
43 #define PIN_OFFSET_FIXED BIT_ULL(7)
45 #define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
46 #define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
/Linux-v5.15/drivers/usb/typec/tipd/
Dtps6598x.h85 #define TPS_REG_INT_USER_VID_ALT_MODE_OTHER_VDM BIT_ULL(27+32)
86 #define TPS_REG_INT_USER_VID_ALT_MODE_ATTN_VDM BIT_ULL(26+32)
87 #define TPS_REG_INT_USER_VID_ALT_MODE_EXIT BIT_ULL(25+32)
88 #define TPS_REG_INT_USER_VID_ALT_MODE_ENTERED BIT_ULL(24+32)
89 #define TPS_REG_INT_EXIT_MODES_COMPLETE BIT_ULL(20+32)
90 #define TPS_REG_INT_DISCOVER_MODES_COMPLETE BIT_ULL(19+32)
91 #define TPS_REG_INT_VDM_MSG_SENT BIT_ULL(18+32)
92 #define TPS_REG_INT_VDM_ENTERED_MODE BIT_ULL(17+32)
93 #define TPS_REG_INT_ERROR_UNABLE_TO_SOURCE BIT_ULL(14+32)
94 #define TPS_REG_INT_SRC_TRANSITION BIT_ULL(10+32)
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/Linux-v5.15/drivers/net/ethernet/intel/iavf/
Diavf_adv_rss.h56 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV4_SA)
58 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV6_SA)
60 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV4_DA)
62 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV6_DA)
64 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_TCP_SRC_PORT)
66 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_TCP_DST_PORT)
68 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_UDP_SRC_PORT)
70 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_UDP_DST_PORT)
72 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_SCTP_SRC_PORT)
74 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_SCTP_DST_PORT)
/Linux-v5.15/drivers/net/ethernet/intel/i40e/
Di40e_type.h193 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
194 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
195 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
196 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
197 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
198 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
199 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
200 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
201 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
202 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
[all …]
/Linux-v5.15/drivers/net/ethernet/freescale/dpaa2/
Ddpmac.h88 #define DPMAC_LINK_OPT_AUTONEG BIT_ULL(0)
89 #define DPMAC_LINK_OPT_HALF_DUPLEX BIT_ULL(1)
90 #define DPMAC_LINK_OPT_PAUSE BIT_ULL(2)
91 #define DPMAC_LINK_OPT_ASYM_PAUSE BIT_ULL(3)
94 #define DPMAC_ADVERTISED_10BASET_FULL BIT_ULL(0)
95 #define DPMAC_ADVERTISED_100BASET_FULL BIT_ULL(1)
96 #define DPMAC_ADVERTISED_1000BASET_FULL BIT_ULL(2)
97 #define DPMAC_ADVERTISED_10000BASET_FULL BIT_ULL(4)
98 #define DPMAC_ADVERTISED_2500BASEX_FULL BIT_ULL(5)
101 #define DPMAC_ADVERTISED_AUTONEG BIT_ULL(3)
/Linux-v5.15/drivers/i2c/busses/
Di2c-octeon-core.h12 #define SW_TWSI_V BIT_ULL(63) /* Valid bit */
13 #define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
14 #define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
15 #define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
77 #define TWSI_INT_ST_INT BIT_ULL(0)
78 #define TWSI_INT_TS_INT BIT_ULL(1)
79 #define TWSI_INT_CORE_INT BIT_ULL(2)
80 #define TWSI_INT_ST_EN BIT_ULL(4)
81 #define TWSI_INT_TS_EN BIT_ULL(5)
82 #define TWSI_INT_CORE_EN BIT_ULL(6)
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