Searched refs:BIT_3 (Results 1 – 23 of 23) sorted by relevance
456 #define BD_WRAP_BACK BIT_3496 #define CF_DIF_SEG_DESCR_ENABLE BIT_3813 #define ECF_SEC_LOGIN BIT_3972 #define TCF_ABORT_TASK_SET BIT_31003 #define AOF_ABTS_RTY_CNT BIT_3 /* Use driver specified retry count. */1199 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */1202 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */1257 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)1262 #define GPDX_LED_GREEN_ON BIT_31395 #define MDBS_NON_PARTIC BIT_3[all …]
106 #define BIT_3 0x8 macro228 #define IDC_HEARTBEAT_FAILURE BIT_3493 #define SRB_LOGIN_NVME_PRLI BIT_3539 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3764 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */770 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */773 #define ISR_RISC_INT BIT_3 /* RISC interrupt */781 #define NVR_DATA_IN BIT_31176 #define FO1_CTIO_RETRY BIT_31355 #define MBX_3 BIT_3[all …]
58 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
180 #define NOTIFY_ACK_FLAGS_TERMINATE BIT_3512 #define CTIO_CRC2_AF_DIF_DSD_ENA BIT_3846 TRC_XFR_RDY = BIT_3,
1130 mb[1] = BIT_2 | BIT_3; in qla24xx_async_gnl()4078 (BIT_4 | BIT_3)) >> 3; in qla2x00_update_fw_options()4080 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()4098 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()4126 ha->fw_options[2] |= BIT_3; in qla2x00_update_fw_options()4151 ha->fw_options[2] |= BIT_3; in qla24xx_update_fw_options()4857 nv->firmware_options[0] = BIT_3 | BIT_1; in qla2x00_nvram_config()4900 nv->firmware_options[0] &= ~BIT_3; in qla2x00_nvram_config()4978 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); in qla2x00_nvram_config()5053 icb->firmware_options[0] &= ~BIT_3; in qla2x00_nvram_config()[all …]
1005 #define QLA2XX_CMD_TIMEOUT BIT_3
665 #define NVME_ENABLE_FLAG BIT_34246 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; in qla24xx_modify_vp_config()6354 } else if (subcode & (BIT_3 | BIT_4)) { in qla83xx_access_control()6642 if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0) in __qla24xx_parse_gpdb()6958 if (options & BIT_3) { in ql26xx_led_config()
1395 options |= BIT_3|BIT_2|BIT_1; in qla2x00_beacon_config_store()1412 options |= BIT_3; in qla2x00_beacon_config_store()
3980 if (rd_reg_dword(®->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()
20 #define BIT_3 0x8 macro123 #define ISP_CFG0_1040A BIT_3 /* ISP1040A */149 #define NV_DATA_IN BIT_3157 #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */174 #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */570 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
1123 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()1703 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)1707 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)1908 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()1922 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()2215 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()2838 pkt->control_flags |= cpu_to_le16(BIT_3); in qla1280_64bit_start_scsi()3093 pkt->control_flags |= cpu_to_le16(BIT_3); in qla1280_32bit_start_scsi()3701 if (pkt->entry_status & BIT_3) in qla1280_error_entry()3721 if (pkt->entry_status & (BIT_3 + BIT_2)) { in qla1280_error_entry()[all …]
1342 arg1 &= ~(BIT_2 | BIT_3); in qlcnic_config_switch_port()1348 arg2 |= (BIT_2 | BIT_3); in qlcnic_config_switch_port()1358 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()1362 arg2 &= ~BIT_3; in qlcnic_config_switch_port()1370 arg1 |= (BIT_3 | BIT_5); in qlcnic_config_switch_port()
198 #define BIT_3 0x8 macro495 #define TA_CTL_BUSY BIT_3
922 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_31317 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
553 if (mbx_out & BIT_3) in qlcnic_83xx_dcb_get_hw_capability()
26 #define QLCNIC_DUMP_ORCRB BIT_3
701 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8; in qlcnic_sriov_set_vf_acl()
1024 #define QLC_83XX_SET_VXLAN_UDP_DPORT BIT_3
384 if (status & BIT_3) in qlcnic_sriov_get_vf_vport_info()
365 #define QLCNIC_ENCAP_INNER_L4_UDP BIT_3
2017 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
84 #define BIT_3 0x8 macro231 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
3546 conn->tcp_timer_scale |= BIT_3; in qla4xxx_copy_from_fwddb_param()3653 SET_BITVAL(sess->entry_state, options, BIT_3); in qla4xxx_copy_to_fwddb_param()3667 SET_BITVAL(sess->discovery_auth_optional, options, BIT_3); in qla4xxx_copy_to_fwddb_param()3676 SET_BITVAL(conn->tcp_timer_scale & BIT_2, options, BIT_3); in qla4xxx_copy_to_fwddb_param()3783 conn->tcp_timer_scale |= BIT_3; in qla4xxx_copy_to_sess_conn_params()
