Searched refs:BIT25 (Results 1 – 13 of 13) sorted by relevance
197 #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */219 #define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */
564 #define HSIMR_GPIO9_INT_EN BIT25573 #define HSISR_GPIO9_INT BIT25751 #define IMR_BCNDOK8 BIT25 /* Beacon Queue DMA OK Interrupt 8 */799 #define PHIMR_TXBCNOK BIT25850 #define UHIMR_TXBCNOK BIT25911 #define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */934 #define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */998 #define RCR_RSVD_BIT25 BIT25 /* Reserved */1556 #define SDIO_HIMR_ATIMEND_MSK BIT251582 #define SDIO_HISR_ATIMEND BIT25
42 #define BIT25 0x02000000 macro
66 #define DYNAMIC_RF_RX_GAIN_TRACK BIT25/* ODM_RF_RX_GAIN_TRACK */
386 #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */408 #define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */436 #define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */
58 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 1); in odm_InbandNoise_Monitor_NSeries()68 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 0); in odm_InbandNoise_Monitor_NSeries()
388 ODM_RF_RX_GAIN_TRACK = BIT25,
56 #define BIT25 0x02000000 macro
35 #define BIT25 0x02000000 macro
44 #define BIT25 0x02000000 macro
51 #define BIT25 0x02000000 macro
136 #define RCR_ACKTXBW (BIT24|BIT25)
753 #define LPFC_SLI4_INTR25 BIT25
