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Searched refs:AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h12173 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 macro
Ddce_11_0_sh_mask.h13437 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 macro
Ddce_10_0_sh_mask.h13431 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 macro
Ddce_11_2_sh_mask.h14053 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 macro
Ddce_12_0_sh_mask.h7019 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h5801 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … macro
Ddcn_2_1_0_sh_mask.h7559 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … macro
Ddcn_3_0_1_sh_mask.h7540 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … macro
Ddcn_1_0_sh_mask.h8154 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … macro
Ddcn_3_1_2_sh_mask.h8087 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … macro
Ddcn_3_0_2_sh_mask.h7369 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … macro
Ddcn_2_0_0_sh_mask.h7827 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … macro
Ddcn_3_0_0_sh_mask.h7472 #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … macro