Home
last modified time | relevance | path

Searched refs:AMDGPU_TILING_GET (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_display.c683 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier()
686 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier()
695 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); in convert_tiling_flags_to_modifier()
759 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | in convert_tiling_flags_to_modifier()
766 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; in convert_tiling_flags_to_modifier()
788 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier()
846 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) in check_tiling_flags_gfx6()
849 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); in check_tiling_flags_gfx6()
Ddce_v6_0.c1936 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1939 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
1940 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1941 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1942 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1943 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
1951 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1955 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
Ddce_v8_0.c1827 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1909 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1912 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1913 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1914 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1915 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1916 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
1925 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
Ddce_v10_0.c1898 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1988 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1991 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1992 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1993 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1994 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1995 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2008 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c1940 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2030 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2033 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2034 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2035 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2036 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2037 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2050 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
Damdgpu_object.c1137 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
/Linux-v5.15/include/uapi/drm/
Damdgpu_drm.h364 #define AMDGPU_TILING_GET(value, field) \ macro
/Linux-v5.15/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c4259 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in fill_gfx8_tiling_info_from_flags()
4262 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_gfx8_tiling_info_from_flags()
4263 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_gfx8_tiling_info_from_flags()
4264 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_gfx8_tiling_info_from_flags()
4265 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in fill_gfx8_tiling_info_from_flags()
4266 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in fill_gfx8_tiling_info_from_flags()
4278 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in fill_gfx8_tiling_info_from_flags()
4284 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in fill_gfx8_tiling_info_from_flags()
9978 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && in dm_check_cursor_fb()
9979 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && in dm_check_cursor_fb()
[all …]