Searched refs:AMDGPU_IRQ_STATE_DISABLE (Results 1 – 24 of 24) sorted by relevance
42 AMDGPU_IRQ_STATE_DISABLE, enumerator
165 AMDGPU_IRQ_STATE_DISABLE); in amdgpu_irq_disable_all()575 state = AMDGPU_IRQ_STATE_DISABLE; in amdgpu_irq_update()
601 case AMDGPU_IRQ_STATE_DISABLE: in si_dma_set_trap_irq_state()617 case AMDGPU_IRQ_STATE_DISABLE: in si_dma_set_trap_irq_state()
1019 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v2_4_set_trap_irq_state()1035 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v2_4_set_trap_irq_state()
1124 case AMDGPU_IRQ_STATE_DISABLE: in cik_sdma_set_trap_irq_state()1140 case AMDGPU_IRQ_STATE_DISABLE: in cik_sdma_set_trap_irq_state()
424 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v9_0_ecc_interrupt_state()476 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v9_0_vm_fault_interrupt_state()
1353 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v3_0_set_trap_irq_state()1369 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v3_0_set_trap_irq_state()
2906 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()2957 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_crtc_vline_interrupt_state()2985 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_hpd_interrupt_state()3100 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v8_0_set_pageflip_interrupt_state()
1047 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v6_0_vm_fault_interrupt_state()
3243 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()3264 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_compute_eop_interrupt_state()3306 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_priv_reg_fault_state()3331 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_priv_inst_fault_state()
2990 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()3019 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_crtc_vline_interrupt_state()3049 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_hpd_irq_state()3127 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v10_0_set_pageflip_irq_state()
3113 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_crtc_vblank_interrupt_state()3142 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_crtc_vline_interrupt_state()3172 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_hpd_irq_state()3250 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v11_0_set_pageflip_irq_state()
72 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v10_0_vm_fault_interrupt_state()
2858 case AMDGPU_IRQ_STATE_DISABLE: in dce_v6_0_set_crtc_vblank_interrupt_state()2893 case AMDGPU_IRQ_STATE_DISABLE: in dce_v6_0_set_hpd_interrupt_state()3008 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v6_0_set_pageflip_interrupt_state()
4733 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()4784 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_compute_eop_interrupt_state()4807 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_priv_reg_fault_state()4832 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_priv_inst_fault_state()
6451 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_gfx_eop_interrupt_state()6490 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_compute_eop_interrupt_state()6511 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_reg_fault_state()6522 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_inst_fault_state()6574 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_cp_ecc_int_state()6619 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_sq_int_state()
1244 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v7_0_vm_fault_interrupt_state()
5710 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()5757 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_compute_eop_interrupt_state()5780 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_priv_reg_fault_state()5799 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_priv_inst_fault_state()5826 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_cp_ecc_error_state()
1406 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v8_0_vm_fault_interrupt_state()
9032 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v10_0_set_gfx_eop_interrupt_state()9085 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v10_0_set_compute_eop_interrupt_state()9185 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v10_0_set_priv_reg_fault_state()9204 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v10_0_set_priv_inst_fault_state()9285 if (state == AMDGPU_IRQ_STATE_DISABLE) { in gfx_v10_0_kiq_set_interrupt_state()
3146 case AMDGPU_IRQ_STATE_DISABLE: in kv_dpm_set_interrupt_state()3163 case AMDGPU_IRQ_STATE_DISABLE: in kv_dpm_set_interrupt_state()
7511 case AMDGPU_IRQ_STATE_DISABLE: in si_dpm_set_interrupt_state()7528 case AMDGPU_IRQ_STATE_DISABLE: in si_dpm_set_interrupt_state()
1194 case AMDGPU_IRQ_STATE_DISABLE: in smu_v13_0_set_irq_state()
1369 case AMDGPU_IRQ_STATE_DISABLE: in smu_v11_0_set_irq_state()