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Searched refs:AMDGPU_GPU_PAGE_ALIGN (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_gart.h38 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) macro
Damdgpu_uvd.h37 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
Damdgpu_vcn.c223 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_vcn_sw_init()
224 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); in amdgpu_vcn_sw_init()
239 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); in amdgpu_vcn_sw_init()
241 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); in amdgpu_vcn_sw_init()
Dvcn_v2_0.c326 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume()
375 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_0_mc_resume()
382 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume_dpg_mode()
469 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1874 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_start_sriov()
Dvcn_v2_5.c390 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume()
439 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_5_mc_resume()
445 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume_dpg_mode()
532 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1189 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_sriov_start()
Dvcn_v3_0.c464 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_mc_resume()
509 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v3_0_mc_resume()
514 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_mc_resume_dpg_mode()
601 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1349 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_start_sriov()
Dvcn_v1_0.c296 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v1_0_mc_resume_spg_mode()
363 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v1_0_mc_resume_dpg_mode()
Damdgpu_uvd.c282 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_uvd_sw_init()
Duvd_v7_0.c822 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); in uvd_v7_0_sriov_start()
Damdgpu_vm.c256 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); in amdgpu_vm_bo_size()