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Searched refs:ADF_CSR_RD (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.15/drivers/crypto/qat/qat_common/
Dadf_pf2vf_msg.c25 reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3); in __adf_enable_vf2pf_interrupts()
32 reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5); in __adf_enable_vf2pf_interrupts()
58 reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3) | in __adf_disable_vf2pf_interrupts()
65 reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5) | in __adf_disable_vf2pf_interrupts()
121 val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); in __adf_iov_putmsg()
137 val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); in __adf_iov_putmsg()
156 val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); in __adf_iov_putmsg()
206 msg = ADF_CSR_RD(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr)); in adf_vf2pf_req_hndl()
Dadf_gen2_hw_data.h29 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
85 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
91 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
Dadf_gen4_hw_data.h28 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
32 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
36 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
Dadf_isr.c87 errsou3 = ADF_CSR_RD(pmisc_addr, ADF_ERRSOU3); in adf_msix_isr_ae()
88 errsou5 = ADF_CSR_RD(pmisc_addr, ADF_ERRSOU5); in adf_msix_isr_ae()
95 errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_ERRMSK3); in adf_msix_isr_ae()
96 errmsk5 = ADF_CSR_RD(pmisc_addr, ADF_ERRMSK5); in adf_msix_isr_ae()
Dicp_qat_hal.h128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
Dadf_vf_isr.c103 msg = ADF_CSR_RD(pmisc_bar_addr, hw_data->get_pf2vf_offset(0)); in adf_pf2vf_bh_handler()
189 v_int = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTSOU_OFFSET); in adf_isr()
192 v_mask = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTMSK_OFFSET); in adf_isr()
Dadf_admin.c122 if (ADF_CSR_RD(mailbox, mb_offset) == 1) { in adf_put_admin_msg_sync()
130 ret = read_poll_timeout(ADF_CSR_RD, status, status == 0, in adf_put_admin_msg_sync()
Dadf_accel_devices.h205 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) macro
Dqat_hal.c453 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
457 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
463 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
/Linux-v5.15/drivers/crypto/qat/qat_c3xxx/
Dadf_c3xxx_hw_data.c125 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
128 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
135 val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i)); in adf_enable_error_correction()
138 val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i)); in adf_enable_error_correction()
/Linux-v5.15/drivers/crypto/qat/qat_c62x/
Dadf_c62x_hw_data.c127 val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
130 val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
137 val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i)); in adf_enable_error_correction()
140 val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i)); in adf_enable_error_correction()
/Linux-v5.15/drivers/crypto/qat/qat_dh895xcc/
Dadf_dh895xcc_hw_data.c145 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
148 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
155 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); in adf_enable_error_correction()
158 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i)); in adf_enable_error_correction()