1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020 Linaro Limited
4 *
5 * Based on original driver:
6 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
7 */
8 #include <linux/bitfield.h>
9 #include <linux/iio/adc/qcom-vadc-common.h>
10 #include <linux/iio/consumer.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/thermal.h>
18
19 /*
20 * Thermal monitoring block consists of 8 (ADC_TM5_NUM_CHANNELS) channels. Each
21 * channel is programmed to use one of ADC channels for voltage comparison.
22 * Voltages are programmed using ADC codes, so we have to convert temp to
23 * voltage and then to ADC code value.
24 *
25 * Configuration of TM channels must match configuration of corresponding ADC
26 * channels.
27 */
28
29 #define ADC5_MAX_CHANNEL 0xc0
30 #define ADC_TM5_NUM_CHANNELS 8
31
32 #define ADC_TM5_STATUS_LOW 0x0a
33
34 #define ADC_TM5_STATUS_HIGH 0x0b
35
36 #define ADC_TM5_NUM_BTM 0x0f
37
38 #define ADC_TM5_ADC_DIG_PARAM 0x42
39
40 #define ADC_TM5_FAST_AVG_CTL (ADC_TM5_ADC_DIG_PARAM + 1)
41 #define ADC_TM5_FAST_AVG_EN BIT(7)
42
43 #define ADC_TM5_MEAS_INTERVAL_CTL (ADC_TM5_ADC_DIG_PARAM + 2)
44 #define ADC_TM5_TIMER1 3 /* 3.9ms */
45
46 #define ADC_TM5_MEAS_INTERVAL_CTL2 (ADC_TM5_ADC_DIG_PARAM + 3)
47 #define ADC_TM5_MEAS_INTERVAL_CTL2_MASK 0xf0
48 #define ADC_TM5_TIMER2 10 /* 1 second */
49 #define ADC_TM5_MEAS_INTERVAL_CTL3_MASK 0xf
50 #define ADC_TM5_TIMER3 4 /* 4 second */
51
52 #define ADC_TM_EN_CTL1 0x46
53 #define ADC_TM_EN BIT(7)
54 #define ADC_TM_CONV_REQ 0x47
55 #define ADC_TM_CONV_REQ_EN BIT(7)
56
57 #define ADC_TM5_M_CHAN_BASE 0x60
58
59 #define ADC_TM5_M_ADC_CH_SEL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 0)
60 #define ADC_TM5_M_LOW_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 1)
61 #define ADC_TM5_M_LOW_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 2)
62 #define ADC_TM5_M_HIGH_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 3)
63 #define ADC_TM5_M_HIGH_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 4)
64 #define ADC_TM5_M_MEAS_INTERVAL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 5)
65 #define ADC_TM5_M_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 6)
66 #define ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK 0xf
67 #define ADC_TM5_M_CTL_CAL_SEL_MASK 0x30
68 #define ADC_TM5_M_CTL_CAL_VAL 0x40
69 #define ADC_TM5_M_EN(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 7)
70 #define ADC_TM5_M_MEAS_EN BIT(7)
71 #define ADC_TM5_M_HIGH_THR_INT_EN BIT(1)
72 #define ADC_TM5_M_LOW_THR_INT_EN BIT(0)
73
74 enum adc5_timer_select {
75 ADC5_TIMER_SEL_1 = 0,
76 ADC5_TIMER_SEL_2,
77 ADC5_TIMER_SEL_3,
78 ADC5_TIMER_SEL_NONE,
79 };
80
81 struct adc_tm5_data {
82 const u32 full_scale_code_volt;
83 unsigned int *decimation;
84 unsigned int *hw_settle;
85 };
86
87 enum adc_tm5_cal_method {
88 ADC_TM5_NO_CAL = 0,
89 ADC_TM5_RATIOMETRIC_CAL,
90 ADC_TM5_ABSOLUTE_CAL
91 };
92
93 struct adc_tm5_chip;
94
95 /**
96 * struct adc_tm5_channel - ADC Thermal Monitoring channel data.
97 * @channel: channel number.
98 * @adc_channel: corresponding ADC channel number.
99 * @cal_method: calibration method.
100 * @prescale: channel scaling performed on the input signal.
101 * @hw_settle_time: the time between AMUX being configured and the
102 * start of conversion.
103 * @iio: IIO channel instance used by this channel.
104 * @chip: ADC TM chip instance.
105 * @tzd: thermal zone device used by this channel.
106 */
107 struct adc_tm5_channel {
108 unsigned int channel;
109 unsigned int adc_channel;
110 enum adc_tm5_cal_method cal_method;
111 unsigned int prescale;
112 unsigned int hw_settle_time;
113 struct iio_channel *iio;
114 struct adc_tm5_chip *chip;
115 struct thermal_zone_device *tzd;
116 };
117
118 /**
119 * struct adc_tm5_chip - ADC Thermal Monitoring properties
120 * @regmap: SPMI ADC5 Thermal Monitoring peripheral register map field.
121 * @dev: SPMI ADC5 device.
122 * @data: software configuration data.
123 * @channels: array of ADC TM channel data.
124 * @nchannels: amount of channels defined/allocated
125 * @decimation: sampling rate supported for the channel.
126 * @avg_samples: ability to provide single result from the ADC
127 * that is an average of multiple measurements.
128 * @base: base address of TM registers.
129 */
130 struct adc_tm5_chip {
131 struct regmap *regmap;
132 struct device *dev;
133 const struct adc_tm5_data *data;
134 struct adc_tm5_channel *channels;
135 unsigned int nchannels;
136 unsigned int decimation;
137 unsigned int avg_samples;
138 u16 base;
139 };
140
141 static const struct adc_tm5_data adc_tm5_data_pmic = {
142 .full_scale_code_volt = 0x70e4,
143 .decimation = (unsigned int []) { 250, 420, 840 },
144 .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700,
145 1000, 2000, 4000, 8000, 16000, 32000,
146 64000, 128000 },
147 };
148
adc_tm5_read(struct adc_tm5_chip * adc_tm,u16 offset,u8 * data,int len)149 static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len)
150 {
151 return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len);
152 }
153
adc_tm5_write(struct adc_tm5_chip * adc_tm,u16 offset,u8 * data,int len)154 static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len)
155 {
156 return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len);
157 }
158
adc_tm5_reg_update(struct adc_tm5_chip * adc_tm,u16 offset,u8 mask,u8 val)159 static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val)
160 {
161 return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val);
162 }
163
adc_tm5_isr(int irq,void * data)164 static irqreturn_t adc_tm5_isr(int irq, void *data)
165 {
166 struct adc_tm5_chip *chip = data;
167 u8 status_low, status_high, ctl;
168 int ret, i;
169
170 ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, sizeof(status_low));
171 if (unlikely(ret)) {
172 dev_err(chip->dev, "read status low failed: %d\n", ret);
173 return IRQ_HANDLED;
174 }
175
176 ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, sizeof(status_high));
177 if (unlikely(ret)) {
178 dev_err(chip->dev, "read status high failed: %d\n", ret);
179 return IRQ_HANDLED;
180 }
181
182 for (i = 0; i < chip->nchannels; i++) {
183 bool upper_set = false, lower_set = false;
184 unsigned int ch = chip->channels[i].channel;
185
186 /* No TZD, we warned at the boot time */
187 if (!chip->channels[i].tzd)
188 continue;
189
190 ret = adc_tm5_read(chip, ADC_TM5_M_EN(ch), &ctl, sizeof(ctl));
191 if (unlikely(ret)) {
192 dev_err(chip->dev, "ctl read failed: %d, channel %d\n", ret, i);
193 continue;
194 }
195
196 if (!(ctl & ADC_TM5_M_MEAS_EN))
197 continue;
198
199 lower_set = (status_low & BIT(ch)) &&
200 (ctl & ADC_TM5_M_LOW_THR_INT_EN);
201
202 upper_set = (status_high & BIT(ch)) &&
203 (ctl & ADC_TM5_M_HIGH_THR_INT_EN);
204
205 if (upper_set || lower_set)
206 thermal_zone_device_update(chip->channels[i].tzd,
207 THERMAL_EVENT_UNSPECIFIED);
208 }
209
210 return IRQ_HANDLED;
211 }
212
adc_tm5_get_temp(void * data,int * temp)213 static int adc_tm5_get_temp(void *data, int *temp)
214 {
215 struct adc_tm5_channel *channel = data;
216 int ret;
217
218 if (!channel || !channel->iio)
219 return -EINVAL;
220
221 ret = iio_read_channel_processed(channel->iio, temp);
222 if (ret < 0)
223 return ret;
224
225 if (ret != IIO_VAL_INT)
226 return -EINVAL;
227
228 return 0;
229 }
230
adc_tm5_disable_channel(struct adc_tm5_channel * channel)231 static int adc_tm5_disable_channel(struct adc_tm5_channel *channel)
232 {
233 struct adc_tm5_chip *chip = channel->chip;
234 unsigned int reg = ADC_TM5_M_EN(channel->channel);
235
236 return adc_tm5_reg_update(chip, reg,
237 ADC_TM5_M_MEAS_EN |
238 ADC_TM5_M_HIGH_THR_INT_EN |
239 ADC_TM5_M_LOW_THR_INT_EN,
240 0);
241 }
242
adc_tm5_enable(struct adc_tm5_chip * chip)243 static int adc_tm5_enable(struct adc_tm5_chip *chip)
244 {
245 int ret;
246 u8 data;
247
248 data = ADC_TM_EN;
249 ret = adc_tm5_write(chip, ADC_TM_EN_CTL1, &data, sizeof(data));
250 if (ret < 0) {
251 dev_err(chip->dev, "adc-tm enable failed\n");
252 return ret;
253 }
254
255 data = ADC_TM_CONV_REQ_EN;
256 ret = adc_tm5_write(chip, ADC_TM_CONV_REQ, &data, sizeof(data));
257 if (ret < 0) {
258 dev_err(chip->dev, "adc-tm request conversion failed\n");
259 return ret;
260 }
261
262 return 0;
263 }
264
adc_tm5_configure(struct adc_tm5_channel * channel,int low,int high)265 static int adc_tm5_configure(struct adc_tm5_channel *channel, int low, int high)
266 {
267 struct adc_tm5_chip *chip = channel->chip;
268 u8 buf[8];
269 u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel);
270 int ret;
271
272 ret = adc_tm5_read(chip, reg, buf, sizeof(buf));
273 if (ret) {
274 dev_err(chip->dev, "channel %d params read failed: %d\n", channel->channel, ret);
275 return ret;
276 }
277
278 buf[0] = channel->adc_channel;
279
280 /* High temperature corresponds to low voltage threshold */
281 if (high != INT_MAX) {
282 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale,
283 chip->data->full_scale_code_volt, high);
284
285 buf[1] = adc_code & 0xff;
286 buf[2] = adc_code >> 8;
287 buf[7] |= ADC_TM5_M_LOW_THR_INT_EN;
288 } else {
289 buf[7] &= ~ADC_TM5_M_LOW_THR_INT_EN;
290 }
291
292 /* Low temperature corresponds to high voltage threshold */
293 if (low != -INT_MAX) {
294 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale,
295 chip->data->full_scale_code_volt, low);
296
297 buf[3] = adc_code & 0xff;
298 buf[4] = adc_code >> 8;
299 buf[7] |= ADC_TM5_M_HIGH_THR_INT_EN;
300 } else {
301 buf[7] &= ~ADC_TM5_M_HIGH_THR_INT_EN;
302 }
303
304 buf[5] = ADC5_TIMER_SEL_2;
305
306 /* Set calibration select, hw_settle delay */
307 buf[6] &= ~ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK;
308 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time);
309 buf[6] &= ~ADC_TM5_M_CTL_CAL_SEL_MASK;
310 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method);
311
312 buf[7] |= ADC_TM5_M_MEAS_EN;
313
314 ret = adc_tm5_write(chip, reg, buf, sizeof(buf));
315 if (ret) {
316 dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret);
317 return ret;
318 }
319
320 return adc_tm5_enable(chip);
321 }
322
adc_tm5_set_trips(void * data,int low,int high)323 static int adc_tm5_set_trips(void *data, int low, int high)
324 {
325 struct adc_tm5_channel *channel = data;
326 struct adc_tm5_chip *chip;
327 int ret;
328
329 if (!channel)
330 return -EINVAL;
331
332 chip = channel->chip;
333 dev_dbg(chip->dev, "%d:low(mdegC):%d, high(mdegC):%d\n",
334 channel->channel, low, high);
335
336 if (high == INT_MAX && low <= -INT_MAX)
337 ret = adc_tm5_disable_channel(channel);
338 else
339 ret = adc_tm5_configure(channel, low, high);
340
341 return ret;
342 }
343
344 static struct thermal_zone_of_device_ops adc_tm5_ops = {
345 .get_temp = adc_tm5_get_temp,
346 .set_trips = adc_tm5_set_trips,
347 };
348
adc_tm5_register_tzd(struct adc_tm5_chip * adc_tm)349 static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm)
350 {
351 unsigned int i;
352 struct thermal_zone_device *tzd;
353
354 for (i = 0; i < adc_tm->nchannels; i++) {
355 adc_tm->channels[i].chip = adc_tm;
356
357 tzd = devm_thermal_zone_of_sensor_register(adc_tm->dev,
358 adc_tm->channels[i].channel,
359 &adc_tm->channels[i],
360 &adc_tm5_ops);
361 if (IS_ERR(tzd)) {
362 if (PTR_ERR(tzd) == -ENODEV) {
363 dev_warn(adc_tm->dev, "thermal sensor on channel %d is not used\n",
364 adc_tm->channels[i].channel);
365 continue;
366 }
367
368 dev_err(adc_tm->dev, "Error registering TZ zone for channel %d: %ld\n",
369 adc_tm->channels[i].channel, PTR_ERR(tzd));
370 return PTR_ERR(tzd);
371 }
372 adc_tm->channels[i].tzd = tzd;
373 }
374
375 return 0;
376 }
377
adc_tm5_init(struct adc_tm5_chip * chip)378 static int adc_tm5_init(struct adc_tm5_chip *chip)
379 {
380 u8 buf[4], channels_available;
381 int ret;
382 unsigned int i;
383
384 ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM,
385 &channels_available, sizeof(channels_available));
386 if (ret) {
387 dev_err(chip->dev, "read failed for BTM channels\n");
388 return ret;
389 }
390
391 for (i = 0; i < chip->nchannels; i++) {
392 if (chip->channels[i].channel >= channels_available) {
393 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
394 return -EINVAL;
395 }
396 }
397
398 buf[0] = chip->decimation;
399 buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN;
400 buf[2] = ADC_TM5_TIMER1;
401 buf[3] = FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL2_MASK, ADC_TM5_TIMER2) |
402 FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL3_MASK, ADC_TM5_TIMER3);
403
404 ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf));
405 if (ret) {
406 dev_err(chip->dev, "block write failed: %d\n", ret);
407 return ret;
408 }
409
410 return ret;
411 }
412
adc_tm5_get_dt_channel_data(struct adc_tm5_chip * adc_tm,struct adc_tm5_channel * channel,struct device_node * node)413 static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm,
414 struct adc_tm5_channel *channel,
415 struct device_node *node)
416 {
417 const char *name = node->name;
418 u32 chan, value, varr[2];
419 int ret;
420 struct device *dev = adc_tm->dev;
421 struct of_phandle_args args;
422
423 ret = of_property_read_u32(node, "reg", &chan);
424 if (ret) {
425 dev_err(dev, "%s: invalid channel number %d\n", name, ret);
426 return ret;
427 }
428
429 if (chan >= ADC_TM5_NUM_CHANNELS) {
430 dev_err(dev, "%s: channel number too big: %d\n", name, chan);
431 return -EINVAL;
432 }
433
434 channel->channel = chan;
435
436 /*
437 * We are tied to PMIC's ADC controller, which always use single
438 * argument for channel number. So don't bother parsing
439 * #io-channel-cells, just enforce cell_count = 1.
440 */
441 ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args);
442 if (ret < 0) {
443 dev_err(dev, "%s: error parsing ADC channel number %d: %d\n", name, chan, ret);
444 return ret;
445 }
446 of_node_put(args.np);
447
448 if (args.args_count != 1 || args.args[0] >= ADC5_MAX_CHANNEL) {
449 dev_err(dev, "%s: invalid ADC channel number %d\n", name, chan);
450 return -EINVAL;
451 }
452 channel->adc_channel = args.args[0];
453
454 channel->iio = devm_of_iio_channel_get_by_name(adc_tm->dev, node, NULL);
455 if (IS_ERR(channel->iio)) {
456 ret = PTR_ERR(channel->iio);
457 if (ret != -EPROBE_DEFER)
458 dev_err(dev, "%s: error getting channel: %d\n", name, ret);
459 return ret;
460 }
461
462 ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
463 if (!ret) {
464 ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
465 if (ret < 0) {
466 dev_err(dev, "%s: invalid pre-scaling <%d %d>\n",
467 name, varr[0], varr[1]);
468 return ret;
469 }
470 channel->prescale = ret;
471 } else {
472 /* 1:1 prescale is index 0 */
473 channel->prescale = 0;
474 }
475
476 ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value);
477 if (!ret) {
478 ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle);
479 if (ret < 0) {
480 dev_err(dev, "%s invalid hw-settle-time-us %d us\n",
481 name, value);
482 return ret;
483 }
484 channel->hw_settle_time = ret;
485 } else {
486 channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
487 }
488
489 if (of_property_read_bool(node, "qcom,ratiometric"))
490 channel->cal_method = ADC_TM5_RATIOMETRIC_CAL;
491 else
492 channel->cal_method = ADC_TM5_ABSOLUTE_CAL;
493
494 return 0;
495 }
496
adc_tm5_get_dt_data(struct adc_tm5_chip * adc_tm,struct device_node * node)497 static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node)
498 {
499 struct adc_tm5_channel *channels;
500 struct device_node *child;
501 u32 value;
502 int ret;
503 struct device *dev = adc_tm->dev;
504
505 adc_tm->nchannels = of_get_available_child_count(node);
506 if (!adc_tm->nchannels)
507 return -EINVAL;
508
509 adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels,
510 sizeof(*adc_tm->channels), GFP_KERNEL);
511 if (!adc_tm->channels)
512 return -ENOMEM;
513
514 channels = adc_tm->channels;
515
516 adc_tm->data = of_device_get_match_data(dev);
517 if (!adc_tm->data)
518 adc_tm->data = &adc_tm5_data_pmic;
519
520 ret = of_property_read_u32(node, "qcom,decimation", &value);
521 if (!ret) {
522 ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation);
523 if (ret < 0) {
524 dev_err(dev, "invalid decimation %d\n", value);
525 return ret;
526 }
527 adc_tm->decimation = ret;
528 } else {
529 adc_tm->decimation = ADC5_DECIMATION_DEFAULT;
530 }
531
532 ret = of_property_read_u32(node, "qcom,avg-samples", &value);
533 if (!ret) {
534 ret = qcom_adc5_avg_samples_from_dt(value);
535 if (ret < 0) {
536 dev_err(dev, "invalid avg-samples %d\n", value);
537 return ret;
538 }
539 adc_tm->avg_samples = ret;
540 } else {
541 adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES;
542 }
543
544 for_each_available_child_of_node(node, child) {
545 ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child);
546 if (ret) {
547 of_node_put(child);
548 return ret;
549 }
550
551 channels++;
552 }
553
554 return 0;
555 }
556
adc_tm5_probe(struct platform_device * pdev)557 static int adc_tm5_probe(struct platform_device *pdev)
558 {
559 struct device_node *node = pdev->dev.of_node;
560 struct device *dev = &pdev->dev;
561 struct adc_tm5_chip *adc_tm;
562 struct regmap *regmap;
563 int ret, irq;
564 u32 reg;
565
566 regmap = dev_get_regmap(dev->parent, NULL);
567 if (!regmap)
568 return -ENODEV;
569
570 ret = of_property_read_u32(node, "reg", ®);
571 if (ret)
572 return ret;
573
574 adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL);
575 if (!adc_tm)
576 return -ENOMEM;
577
578 adc_tm->regmap = regmap;
579 adc_tm->dev = dev;
580 adc_tm->base = reg;
581
582 irq = platform_get_irq(pdev, 0);
583 if (irq < 0) {
584 dev_err(dev, "get_irq failed: %d\n", irq);
585 return irq;
586 }
587
588 ret = adc_tm5_get_dt_data(adc_tm, node);
589 if (ret) {
590 dev_err(dev, "get dt data failed: %d\n", ret);
591 return ret;
592 }
593
594 ret = adc_tm5_init(adc_tm);
595 if (ret) {
596 dev_err(dev, "adc-tm init failed\n");
597 return ret;
598 }
599
600 ret = adc_tm5_register_tzd(adc_tm);
601 if (ret) {
602 dev_err(dev, "tzd register failed\n");
603 return ret;
604 }
605
606 return devm_request_threaded_irq(dev, irq, NULL, adc_tm5_isr,
607 IRQF_ONESHOT, "pm-adc-tm5", adc_tm);
608 }
609
610 static const struct of_device_id adc_tm5_match_table[] = {
611 {
612 .compatible = "qcom,spmi-adc-tm5",
613 .data = &adc_tm5_data_pmic,
614 },
615 { }
616 };
617 MODULE_DEVICE_TABLE(of, adc_tm5_match_table);
618
619 static struct platform_driver adc_tm5_driver = {
620 .driver = {
621 .name = "qcom-spmi-adc-tm5",
622 .of_match_table = adc_tm5_match_table,
623 },
624 .probe = adc_tm5_probe,
625 };
626 module_platform_driver(adc_tm5_driver);
627
628 MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver");
629 MODULE_LICENSE("GPL v2");
630
