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/Linux-v5.10/fs/unicode/
Dutf8data.h_shipped97 0xe1,0x8d,0xa9,0x10,0x08,0x01,0xff,0xe8,0xb1,0x88,0x00,0x01,0xff,0xe6,0x9b,0xb4,
99 0xab,0x10,0x08,0x01,0xff,0xe9,0xb9,0xbf,0x00,0x01,0xff,0xe8,0xab,0x96,0x00,0xe3,
100 0x09,0xac,0xe2,0xe8,0xab,0xe1,0xd7,0xab,0x10,0x08,0x01,0xff,0xe7,0xb8,0xb7,0x00,
110 0x4e,0xe3,0xe2,0x2d,0xe3,0xe1,0x1b,0xe3,0x10,0x08,0x05,0xff,0xe4,0xb8,0xbd,0x00,
112 0xe2,0x0e,0xe5,0xe1,0xfd,0xe4,0x10,0x08,0x05,0xff,0xe5,0x92,0xa2,0x00,0x05,0xff,
113 0xe5,0x93,0xb6,0x00,0xd4,0x34,0xd3,0x18,0xe2,0xf7,0xe5,0xe1,0xe6,0xe5,0x10,0x09,
115 0xe6,0x91,0x11,0x10,0x09,0x05,0xff,0xf0,0xa1,0x8d,0xaa,0x00,0x05,0xff,0xe5,0xac,
117 0x10,0x08,0x05,0xff,0xe5,0xaf,0xb3,0x00,0x05,0xff,0xf0,0xa1,0xac,0x98,0x00,0xe1,
118 0x38,0xe6,0x10,0x08,0x05,0xff,0xe5,0xbc,0xb3,0x00,0x05,0xff,0xe5,0xb0,0xa2,0x00,
120 0xea,0xe1,0x93,0xea,0x10,0x08,0x05,0xff,0xe6,0xb4,0xbe,0x00,0x05,0xff,0xe6,0xb5,
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dam335x-pocketbeagle.dts220 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
221 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
229 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
230 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
238 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
239 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
247 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
248 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
256 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
257 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
[all …]
Dimx6qdl-aristainetos.dtsi296 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10
323 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
324 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
325 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
326 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
328 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
329 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
330 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
331 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
332 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
[all …]
Dimx6q-kp.dtsi287 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
288 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
289 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
290 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
291 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
292 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
293 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
294 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
295 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
296 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6qdl-tx6.dtsi395 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
396 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
397 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
398 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
400 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
401 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
402 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
403 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
404 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
405 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
[all …]
Dimx6ul-tx6ul.dtsi621 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
622 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
623 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
624 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
626 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
627 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
628 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
629 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
630 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
631 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
[all …]
Dimx6ul-tx6ul-mainboard.dts203 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
204 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
205 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
206 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
207 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
208 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
209 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
210 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
211 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
212 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
[all …]
Dimx6dl-mamoj.dts401 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */
402 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
403 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */
404 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */
405 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */
406 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
407 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
408 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
409 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
410 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
[all …]
Dimx6qdl-pico.dtsi466 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
467 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
468 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
469 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
470 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10
471 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
472 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
473 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
474 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
475 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
[all …]
Dimx6qdl-nitrogen6x.dtsi450 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
451 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
452 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
453 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
454 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
455 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
456 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
457 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
458 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
459 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6dl-yapp4-common.dtsi417 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
418 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
419 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
420 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
421 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
422 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
423 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
424 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
425 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
426 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
[all …]
Dimx6qdl-emcon.dtsi577 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
578 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
579 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
580 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
581 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
582 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
583 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
584 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
585 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
586 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6qdl-nitrogen6_som2.dtsi442 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
443 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
444 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
445 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
446 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
447 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
448 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
449 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
450 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
451 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6qdl-nitrogen6_max.dtsi529 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
530 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
531 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
532 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
533 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
534 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
535 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
536 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
537 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
538 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6qdl-sabrelite.dtsi544 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
545 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
546 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
547 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
548 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
549 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
550 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
551 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
552 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
553 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dtegra30-cpu-opp.dtsi143 <0x10 0x0080>, <0x02 0x0100>,
145 <0x10 0x0100>;
160 <0x10 0x0080>, <0x08 0x0100>,
161 <0x10 0x0100>, <0x01 0x0400>;
214 <0x08 0x0080>, <0x10 0x0080>,
216 <0x10 0x0100>;
254 <0x08 0x0080>, <0x10 0x0080>,
256 <0x10 0x0100>;
283 <0x10 0x0080>, <0x08 0x0100>,
284 <0x10 0x0100>;
[all …]
/Linux-v5.10/drivers/scsi/aic7xxx/
Daic79xx_reg_print.c_shipped16 { "PCIINT", 0x10, 0x10 },
47 { "SEQ_SWTMRTO", 0x10, 0x10 }
62 { "AUTOCLRCMDINT", 0x10, 0x10 },
101 { "MREQPEND", 0x10, 0x10 },
129 { "FORCEBUSFREE", 0x10, 0x10 },
146 { "ENRSELI", 0x10, 0x10 },
162 { "FIFO0FREE", 0x10, 0x10 },
187 { "ATNI", 0x10, 0x10 },
207 { "COMMAND_PHASE", 0x10, 0x10 },
242 { "ENSELINGO", 0x10, 0x10 },
[all …]
Daic7xxx_reg_print.c_shipped16 { "ENRSELI", 0x10, 0x10 },
33 { "CLRSTCNT", 0x10, 0x10 },
51 { "ATNI", 0x10, 0x10 },
74 { "SINGLE_EDGE", 0x10, 0x10 },
95 { "SELINGO", 0x10, 0x10 },
113 { "PHASEMIS", 0x10, 0x10 },
131 { "EXP_ACTIVE", 0x10, 0x10 },
163 { "ENSELINGO", 0x10, 0x10 },
172 0x10, regvalue, cur_col, wrap));
180 { "ENPHASEMIS", 0x10, 0x10 },
[all …]
Daic7xxx_reg.h_shipped75 ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap)
199 #define CLRSTCNT 0x10
216 #define ATNO 0x10
225 #define ATNI 0x10
237 #define SINGLE_EDGE 0x10
252 #define BUSFREEREV 0x10
265 #define CLRSELINGO 0x10
274 #define SELINGO 0x10
294 #define PHASEMIS 0x10
304 #define EXP_ACTIVE 0x10
[all …]
Daic79xx_reg.h_shipped375 #define PCIINT 0x10
392 #define STATUS_OVERRUN 0x10
414 #define CLRPCIINT 0x10
424 #define CLRDPARERR 0x10
433 #define DPARERR 0x10
441 #define SWINT 0x10
457 #define SEQ_SWTMRTO 0x10
464 #define CLRSEQ_SWTMRTO 0x10
472 #define SNSCB_QOFF 0x10
482 #define HS_MAILBOX_ACT 0x10
[all …]
/Linux-v5.10/arch/arm64/mm/
Dproc.S78 mrs x10, oslsr_el1
90 stp x10, x11, [x0, #64]
110 ldp x9, x10, [x0, #48]
139 msr mdscr_el1, x10
238 pud .req x10
434 mrs x10, ID_AA64PFR1_EL1
435 ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
436 cmp x10, #ID_AA64PFR1_MTE
440 mov x10, #MAIR_ATTR_NORMAL_TAGGED
441 bfi x5, x10, #(8 * MT_NORMAL_TAGGED), #8
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/
Dresource-names.txt31 reg = <0 0x10 0x10>, <0 0x20 0x10>,
32 <1 0x10 0x10>, <1 0x20 0x10>;
41 reg = <0 0x40 0x10>, <1 0x40 0x10>;
/Linux-v5.10/arch/arm64/crypto/
Dpoly1305-core.S_shipped103 ldp x10,x11,[x1],#16 // load input
106 rev x10,x10
109 adds x4,x4,x10 // accumulate input
116 mul x10,x5,x9 // h1*5*r1
119 adds x12,x12,x10
120 mul x10,x4,x8 // h0*r1
124 adds x13,x13,x10
125 mul x10,x5,x7 // h1*r0
129 adds x13,x13,x10
130 mul x10,x6,x9 // h2*5*r1
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dmdio-mux-gpio.txt41 marvell,reg-init = <3 0x10 0 0x5777>,
50 marvell,reg-init = <3 0x10 0 0x5777>,
59 marvell,reg-init = <3 0x10 0 0x5777>,
68 marvell,reg-init = <3 0x10 0 0x5777>,
84 marvell,reg-init = <3 0x10 0 0x5777>,
93 marvell,reg-init = <3 0x10 0 0x5777>,
102 marvell,reg-init = <3 0x10 0 0x5777>,
111 marvell,reg-init = <3 0x10 0 0x5777>,
Dmdio-mux.txt51 marvell,reg-init = <3 0x10 0 0x5777>,
60 marvell,reg-init = <3 0x10 0 0x5777>,
69 marvell,reg-init = <3 0x10 0 0x5777>,
78 marvell,reg-init = <3 0x10 0 0x5777>,
94 marvell,reg-init = <3 0x10 0 0x5777>,
103 marvell,reg-init = <3 0x10 0 0x5777>,
112 marvell,reg-init = <3 0x10 0 0x5777>,
121 marvell,reg-init = <3 0x10 0 0x5777>,

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