/Linux-v5.10/arch/x86/hyperv/ |
D | hv_init.c | 111 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, val); in hv_cpu_init() 138 wrmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); in hyperv_stop_tsc_emulation() 182 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in set_hv_tscchange_cb() 183 wrmsrl(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl)); in set_hv_tscchange_cb() 196 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); in clear_hv_tscchange_cb() 218 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, 0); in hv_cpu_die() 237 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in hv_cpu_die() 277 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_suspend() 296 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_resume() 376 wrmsrl(HV_X64_MSR_GUEST_OS_ID, guest_id); in hyperv_init() [all …]
|
/Linux-v5.10/arch/x86/oprofile/ |
D | op_model_amd.c | 156 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); in op_amd_handle_ibs() 185 wrmsrl(MSR_AMD64_IBSOPCTL, ctl); in op_amd_handle_ibs() 211 wrmsrl(MSR_AMD64_IBSFETCHCTL, val); in op_amd_start_ibs() 248 wrmsrl(MSR_AMD64_IBSOPCTL, val); in op_amd_start_ibs() 259 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); in op_amd_stop_ibs() 263 wrmsrl(MSR_AMD64_IBSOPCTL, 0); in op_amd_stop_ibs() 282 wrmsrl(msrs->controls[i].addr, val); in op_mux_switch_ctrl() 356 wrmsrl(msrs->controls[i].addr, val); in op_amd_setup_ctrs() 361 wrmsrl(msrs->counters[i].addr, -1LL); in op_amd_setup_ctrs() 371 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); in op_amd_setup_ctrs() [all …]
|
D | op_model_ppro.c | 103 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs() 108 wrmsrl(msrs->counters[i].addr, -1LL); in ppro_setup_ctrs() 115 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_setup_ctrs() 119 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs() 140 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_check_ctrs() 167 wrmsrl(msrs->controls[i].addr, val); in ppro_start() 183 wrmsrl(msrs->controls[i].addr, val); in ppro_stop()
|
/Linux-v5.10/arch/x86/events/intel/ |
D | uncore_nhmex.c | 202 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); in nhmex_uncore_msr_init_box() 207 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); in nhmex_uncore_msr_exit_box() 221 wrmsrl(msr, config); in nhmex_uncore_msr_disable_box() 236 wrmsrl(msr, config); in nhmex_uncore_msr_enable_box() 242 wrmsrl(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event() 250 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event() 252 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event() 254 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event() 384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event() 385 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event() [all …]
|
D | uncore_snb.c | 146 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event() 148 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event() 153 wrmsrl(event->hw.config_base, 0); in snb_uncore_msr_disable_event() 159 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_init_box() 166 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_enable_box() 173 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); in snb_uncore_msr_exit_box() 258 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_init_box() 269 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_enable_box() 276 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); in skl_uncore_msr_exit_box() 1084 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0); in nhm_uncore_msr_disable_box() [all …]
|
D | lbr.c | 207 wrmsrl(MSR_LBR_SELECT, lbr_select); in __intel_pmu_lbr_enable() 225 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_enable() 228 wrmsrl(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN); in __intel_pmu_lbr_enable() 236 wrmsrl(MSR_ARCH_LBR_CTL, 0); in __intel_pmu_lbr_disable() 242 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_disable() 250 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32() 258 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64() 259 wrmsrl(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64() 261 wrmsrl(x86_pmu.lbr_info + i, 0); in intel_pmu_lbr_reset_64() 268 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); in intel_pmu_arch_lbr_reset() [all …]
|
D | knc.c | 164 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_disable_all() 173 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_enable_all() 210 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack); in knc_pmu_ack_status()
|
D | p6.c | 145 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_disable_all() 155 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_enable_all()
|
/Linux-v5.10/arch/x86/include/asm/ |
D | mshyperv.h | 18 wrmsrl(HV_X64_MSR_STIMER0_COUNT + (2*timer), tick) 20 wrmsrl(HV_X64_MSR_STIMER0_CONFIG + (2*timer), val) 23 #define hv_set_simp(val) wrmsrl(HV_X64_MSR_SIMP, val) 26 #define hv_set_siefp(val) wrmsrl(HV_X64_MSR_SIEFP, val) 29 #define hv_set_synic_state(val) wrmsrl(HV_X64_MSR_SCONTROL, val) 33 #define hv_signal_eom() wrmsrl(HV_X64_MSR_EOM, 0) 38 wrmsrl(HV_X64_MSR_SINT0 + int_num, val) 51 wrmsrl(HV_X64_MSR_REFERENCE_TSC, val)
|
D | virtext.h | 114 wrmsrl(MSR_VM_HSAVE_PA, 0); in cpu_svm_disable() 116 wrmsrl(MSR_EFER, efer & ~EFER_SVME); in cpu_svm_disable()
|
D | fsgsbase.h | 73 wrmsrl(MSR_FS_BASE, fsbase); in x86_fsbase_write_cpu()
|
/Linux-v5.10/arch/x86/kernel/cpu/mce/ |
D | inject.c | 462 wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); in prepare_msrs() 466 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); in prepare_msrs() 467 wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); in prepare_msrs() 469 wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); in prepare_msrs() 470 wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); in prepare_msrs() 473 wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); in prepare_msrs() 474 wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); in prepare_msrs() 476 wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); in prepare_msrs() 477 wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); in prepare_msrs() 478 wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); in prepare_msrs()
|
D | intel.c | 171 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode() 309 wrmsrl(MSR_IA32_MCx_CTL2(i), val); in cmci_discover() 364 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank() 458 wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); in intel_init_lmce() 470 wrmsrl(MSR_IA32_MCG_EXT_CTL, val); in intel_clear_lmce()
|
/Linux-v5.10/arch/x86/power/ |
D | cpu.c | 55 wrmsrl(msr->info.msr_no, msr->info.reg.q); in msr_restore_context() 199 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); in __restore_processor_state() 209 wrmsrl(MSR_EFER, ctxt->efer); in __restore_processor_state() 232 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); in __restore_processor_state() 256 wrmsrl(MSR_FS_BASE, ctxt->fs_base); in __restore_processor_state() 257 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); in __restore_processor_state()
|
/Linux-v5.10/arch/x86/kernel/ |
D | kvm.c | 284 wrmsrl(MSR_KVM_ASYNC_PF_ACK, 1); in DEFINE_IDTENTRY_SYSVEC() 310 wrmsrl(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); in kvm_register_steal_time() 344 wrmsrl(MSR_KVM_ASYNC_PF_INT, HYPERVISOR_CALLBACK_VECTOR); in kvm_guest_cpu_init() 346 wrmsrl(MSR_KVM_ASYNC_PF_EN, pa); in kvm_guest_cpu_init() 359 wrmsrl(MSR_KVM_PV_EOI_EN, pa); in kvm_guest_cpu_init() 371 wrmsrl(MSR_KVM_ASYNC_PF_EN, 0); in kvm_pv_disable_apf() 385 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_pv_guest_cpu_reboot() 594 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_guest_cpu_offline() 952 wrmsrl(MSR_KVM_POLL_CONTROL, 0); in kvm_disable_host_haltpoll() 957 wrmsrl(MSR_KVM_POLL_CONTROL, 1); in kvm_enable_host_haltpoll()
|
D | process.c | 258 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); in set_cpuid_faulting() 473 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state() 490 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state() 500 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state() 509 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state() 519 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); in amd_set_ssb_virt_state() 558 wrmsrl(MSR_IA32_SPEC_CTRL, msr); in __speculation_ctrl_update() 626 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __switch_to_xtra()
|
D | tsc_sync.c | 71 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); in tsc_verify_tsc_adjust() 103 wrmsrl(MSR_IA32_TSC_ADJUST, 0); in tsc_sanitize_first_cpu() 192 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted); in tsc_store_and_check_tsc_adjust() 488 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted); in check_tsc_sync_target()
|
/Linux-v5.10/arch/x86/xen/ |
D | suspend.c | 44 wrmsrl(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); in xen_vcpu_notify_restore() 62 wrmsrl(MSR_IA32_SPEC_CTRL, 0); in xen_vcpu_notify_suspend()
|
/Linux-v5.10/drivers/video/fbdev/geode/ |
D | video_gx.c | 154 wrmsrl(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency() 162 wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); in gx_set_dclk_frequency() 166 wrmsrl(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency() 186 wrmsrl(MSR_GX_MSR_PADSEL, val); in gx_configure_tft()
|
/Linux-v5.10/arch/x86/kernel/cpu/ |
D | tsx.c | 39 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_disable() 58 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_enable()
|
D | bugs.c | 182 wrmsrl(MSR_IA32_SPEC_CTRL, msrval); in x86_virt_spec_ctrl() 223 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); in x86_amd_ssb_disable() 225 wrmsrl(MSR_AMD64_LS_CFG, msrval); in x86_amd_ssb_disable() 453 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); in update_srbds_msr() 883 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); in spectre_v2_select_mitigation() 959 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); in update_stibp_msr() 1183 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); in __ssb_select_mitigation() 1401 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); in x86_spec_ctrl_setup_ap()
|
/Linux-v5.10/drivers/cpufreq/ |
D | longhaul.c | 147 wrmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1() 156 wrmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1() 183 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver() 197 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver() 202 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver() 215 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver() 220 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver() 234 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
|
/Linux-v5.10/arch/x86/events/zhaoxin/ |
D | core.c | 257 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); in zhaoxin_pmu_disable_all() 262 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); in zhaoxin_pmu_enable_all() 276 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); in zhaoxin_pmu_ack_status() 298 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed() 335 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
|
/Linux-v5.10/drivers/platform/x86/intel_speed_select_if/ |
D | isst_if_mbox_msr.c | 57 wrmsrl(MSR_OS_MAILBOX_DATA, command_data); in isst_if_send_mbox_cmd() 64 wrmsrl(MSR_OS_MAILBOX_INTERFACE, data); in isst_if_send_mbox_cmd()
|
/Linux-v5.10/drivers/platform/x86/ |
D | intel_ips.c | 384 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_cpu_raise() 389 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_cpu_raise() 419 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_cpu_lower() 424 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_cpu_lower() 442 wrmsrl(IA32_PERF_CTL, perf_ctl); in do_enable_cpu_turbo() 480 wrmsrl(IA32_PERF_CTL, perf_ctl); in do_disable_cpu_turbo() 1617 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); in ips_remove() 1618 wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); in ips_remove()
|