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Searched refs:wr32 (Results 1 – 25 of 85) sorted by relevance

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/Linux-v5.10/drivers/net/ethernet/intel/igc/
Digc_tsn.c35 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT); in igc_tsn_disable_offload()
36 wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_DEFAULT); in igc_tsn_disable_offload()
41 wr32(IGC_TQAVCTRL, tqavctrl); in igc_tsn_disable_offload()
50 wr32(IGC_TXQCTL(i), 0); in igc_tsn_disable_offload()
51 wr32(IGC_STQT(i), 0); in igc_tsn_disable_offload()
52 wr32(IGC_ENDQT(i), NSEC_PER_SEC); in igc_tsn_disable_offload()
55 wr32(IGC_QBVCYCLET_S, NSEC_PER_SEC); in igc_tsn_disable_offload()
56 wr32(IGC_QBVCYCLET, NSEC_PER_SEC); in igc_tsn_disable_offload()
77 wr32(IGC_TSAUXC, 0); in igc_tsn_enable_offload()
78 wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN); in igc_tsn_enable_offload()
[all …]
Digc_base.c32 wr32(IGC_IMC, 0xffffffff); in igc_reset_hw_base()
34 wr32(IGC_RCTL, 0); in igc_reset_hw_base()
35 wr32(IGC_TCTL, IGC_TCTL_PSP); in igc_reset_hw_base()
43 wr32(IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); in igc_reset_hw_base()
55 wr32(IGC_IMC, 0xffffffff); in igc_reset_hw_base()
116 wr32(IGC_CTRL, ctrl); in igc_setup_copper_link_base()
353 wr32(IGC_RFCTL, rfctl); in igc_rx_fifo_flush_base()
361 wr32(IGC_RXDCTL(i), in igc_rx_fifo_flush_base()
381 wr32(IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF); in igc_rx_fifo_flush_base()
384 wr32(IGC_RLPML, 0); in igc_rx_fifo_flush_base()
[all …]
Digc_diag.c46 wr32(reg, test_pattern[pat] & write); in reg_pattern_test()
53 wr32(reg, before); in reg_pattern_test()
56 wr32(reg, before); in reg_pattern_test()
68 wr32(reg, write & mask); in reg_set_and_check()
75 wr32(reg, before); in reg_set_and_check()
78 wr32(reg, before); in reg_set_and_check()
97 wr32(IGC_STATUS, toggle); in igc_reg_test()
107 wr32(IGC_STATUS, before); in igc_reg_test()
Digc_ptp.c38 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
39 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
63 wr32(IGC_TIMINCA, inca); in igc_ptp_adjfine_i225()
206 wr32(IGC_TSYNCRXCTL, 0); in igc_ptp_disable_rx_timestamp()
211 wr32(IGC_SRRCTL(i), val); in igc_ptp_disable_rx_timestamp()
216 wr32(IGC_RXPBS, val); in igc_ptp_disable_rx_timestamp()
227 wr32(IGC_RXPBS, val); in igc_ptp_enable_rx_timestamp()
236 wr32(IGC_SRRCTL(i), val); in igc_ptp_enable_rx_timestamp()
241 wr32(IGC_TSYNCRXCTL, val); in igc_ptp_enable_rx_timestamp()
248 wr32(IGC_TSYNCTXCTL, 0); in igc_ptp_disable_tx_timestamp()
[all …]
Digc_mac.c29 wr32(IGC_CTRL, ctrl); in igc_disable_pcie_master()
103 wr32(IGC_FCRTL, fcrtl); in igc_set_fc_watermarks()
104 wr32(IGC_FCRTH, fcrth); in igc_set_fc_watermarks()
154 wr32(IGC_FCT, FLOW_CONTROL_TYPE); in igc_setup_link()
155 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); in igc_setup_link()
156 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igc_setup_link()
158 wr32(IGC_FCTTV, hw->fc.pause_time); in igc_setup_link()
223 wr32(IGC_CTRL, ctrl); in igc_force_mac_fc()
341 wr32(IGC_RAL(index), rar_low); in igc_rar_set()
343 wr32(IGC_RAH(index), rar_high); in igc_rar_set()
[all …]
Digc_i225.c82 wr32(IGC_SWSM, swsm | IGC_SWSM_SWESMBI); in igc_get_hw_semaphore_i225()
140 wr32(IGC_SW_FW_SYNC, swfw_sync); in igc_acquire_swfw_sync_i225()
164 wr32(IGC_SW_FW_SYNC, swfw_sync); in igc_release_swfw_sync_i225()
241 wr32(IGC_SRWR, eewr); in igc_write_nvm_srwr()
377 wr32(IGC_EECD, flup); in igc_update_flash_i225()
540 wr32(IGC_IPCNFG, ipcnfg); in igc_set_eee_i225()
541 wr32(IGC_EEER, eeer); in igc_set_eee_i225()
573 wr32(IGC_LTRC, ltrc); in igc_set_ltr_i225()
634 wr32(IGC_LTRMINV, ltrv); in igc_set_ltr_i225()
641 wr32(IGC_LTRMAXV, ltrv); in igc_set_ltr_i225()
Digc_nvm.c52 wr32(IGC_EECD, eecd | IGC_EECD_REQ); in igc_acquire_nvm()
65 wr32(IGC_EECD, eecd); in igc_acquire_nvm()
85 wr32(IGC_EECD, eecd); in igc_release_nvm()
117 wr32(IGC_EERD, eerd); in igc_read_nvm_eerd()
Digc_main.c143 wr32(IGC_CTRL_EXT, in igc_release_hw_control()
162 wr32(IGC_CTRL_EXT, in igc_get_hw_control()
516 wr32(IGC_RXDCTL(reg_idx), 0); in igc_configure_rx_ring()
519 wr32(IGC_RDBAL(reg_idx), in igc_configure_rx_ring()
521 wr32(IGC_RDBAH(reg_idx), rdba >> 32); in igc_configure_rx_ring()
522 wr32(IGC_RDLEN(reg_idx), in igc_configure_rx_ring()
527 wr32(IGC_RDH(reg_idx), 0); in igc_configure_rx_ring()
542 wr32(IGC_SRRCTL(reg_idx), srrctl); in igc_configure_rx_ring()
559 wr32(IGC_RXDCTL(reg_idx), rxdctl); in igc_configure_rx_ring()
595 wr32(IGC_TXDCTL(reg_idx), 0); in igc_configure_tx_ring()
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/igb/
Digb_ptp.c139 wr32(E1000_SYSTIML, ts->tv_nsec); in igb_ptp_write_i210()
140 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); in igb_ptp_write_i210()
218 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); in igb_ptp_adjfreq_82576()
244 wr32(E1000_TIMINCA, inca); in igb_ptp_adjfine_82580()
439 wr32(E1000_TSSDP, tssdp); in igb_pin_extts()
440 wr32(E1000_CTRL, ctrl); in igb_pin_extts()
441 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pin_extts()
505 wr32(E1000_TSSDP, tssdp); in igb_pin_perout()
506 wr32(E1000_CTRL, ctrl); in igb_pin_perout()
507 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pin_perout()
[all …]
De1000_82575.c202 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_init_phy_params_82575()
504 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); in igb_set_sfp_media_type_82575()
550 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_set_sfp_media_type_82575()
668 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_invariants_82575()
874 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); in igb_get_phy_id_82575()
906 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_phy_id_82575()
1062 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d0_lplu_state_82580()
1106 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d3_lplu_state_82580()
1190 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_82575()
1215 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_82575()
[all …]
De1000_mac.c243 wr32(E1000_VLVF(vlvf_index), 0); in igb_vfta_set()
266 wr32(E1000_VLVF(vlvf_index), bits | vlan | E1000_VLVF_VLANID_ENABLE); in igb_vfta_set()
377 wr32(E1000_RAL(index), rar_low); in igb_rar_set()
379 wr32(E1000_RAH(index), rar_high); in igb_rar_set()
685 wr32(E1000_FCT, FLOW_CONTROL_TYPE); in igb_setup_link()
686 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); in igb_setup_link()
687 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igb_setup_link()
689 wr32(E1000_FCTTV, hw->fc.pause_time); in igb_setup_link()
715 wr32(E1000_TCTL, tctl); in igb_config_collision_dist()
748 wr32(E1000_FCRTL, fcrtl); in igb_set_fc_watermarks()
[all …]
De1000_i210.c64 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); in igb_get_hw_semaphore_i210()
148 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_i210()
172 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_i210()
250 wr32(E1000_SRWR, eewr); in igb_write_nvm_srwr()
679 wr32(E1000_EECD, flup); in igb_update_flash_i210()
837 wr32(E1000_MDICNFG, reg_val); in igb_pll_workaround_i210()
859 wr32(E1000_CTRL, ctrl|E1000_CTRL_PHY_RST); in igb_pll_workaround_i210()
863 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pll_workaround_i210()
865 wr32(E1000_WUC, 0); in igb_pll_workaround_i210()
867 wr32(E1000_EEARBC_I210, reg_val); in igb_pll_workaround_i210()
[all …]
Digb_main.c587 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_data()
612 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_clk()
885 wr32(E1000_CTRL_EXT, tmp); in igb_configure_msix()
902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | in igb_configure_msix()
910 wr32(E1000_IVAR_MISC, tmp); in igb_configure_msix()
1143 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); in igb_set_interrupt_capability()
1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1481 wr32(E1000_EIMC, adapter->eims_enable_mask); in igb_irq_disable()
1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1486 wr32(E1000_IAM, 0); in igb_irq_disable()
[all …]
De1000_mbx.c249 wr32(E1000_MBVFICR, mask); in igb_check_for_bit_pf()
307 wr32(E1000_VFLRE, BIT(vf_number)); in igb_check_for_rst_pf()
329 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU); in igb_obtain_mbx_lock_pf()
357 wr32(E1000_P2VMAILBOX(vf_number), in igb_release_mbx_lock_pf()
392 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS); in igb_write_mbx_pf()
431 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK); in igb_read_mbx_pf()
433 wr32(E1000_P2VMAILBOX(vf_number), in igb_read_mbx_pf()
De1000_nvm.c20 wr32(E1000_EECD, *eecd); in igb_raise_eec_clk()
35 wr32(E1000_EECD, *eecd); in igb_lower_eec_clk()
66 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
78 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
165 wr32(E1000_EECD, eecd | E1000_EECD_REQ); in igb_acquire_nvm()
178 wr32(E1000_EECD, eecd); in igb_acquire_nvm()
200 wr32(E1000_EECD, eecd); in igb_standby_nvm()
204 wr32(E1000_EECD, eecd); in igb_standby_nvm()
242 wr32(E1000_EECD, eecd); in igb_release_nvm()
263 wr32(E1000_EECD, eecd); in igb_ready_nvm_eeprom()
[all …]
Digb_ethtool.c1223 wr32(reg, (_test[pat] & write)); in reg_pattern_test()
1243 wr32(reg, write & mask); in reg_set_and_check()
1307 wr32(E1000_STATUS, toggle); in igb_reg_test()
1317 wr32(E1000_STATUS, before); in igb_reg_test()
1435 wr32(E1000_IMC, ~0); in igb_intr_test()
1479 wr32(E1000_ICR, ~0); in igb_intr_test()
1481 wr32(E1000_IMC, mask); in igb_intr_test()
1482 wr32(E1000_ICS, mask); in igb_intr_test()
1501 wr32(E1000_ICR, ~0); in igb_intr_test()
1503 wr32(E1000_IMS, mask); in igb_intr_test()
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/iavf/
Diavf_adminq.c262 wr32(hw, hw->aq.asq.head, 0); in iavf_config_asq_regs()
263 wr32(hw, hw->aq.asq.tail, 0); in iavf_config_asq_regs()
266 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in iavf_config_asq_regs()
268 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); in iavf_config_asq_regs()
269 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); in iavf_config_asq_regs()
291 wr32(hw, hw->aq.arq.head, 0); in iavf_config_arq_regs()
292 wr32(hw, hw->aq.arq.tail, 0); in iavf_config_arq_regs()
295 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in iavf_config_arq_regs()
297 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); in iavf_config_arq_regs()
298 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); in iavf_config_arq_regs()
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/i40e/
Di40e_hmc.h108 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
109 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
110 wr32((hw), I40E_PFHMC_SDCMD, val3); \
127 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
128 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
129 wr32((hw), I40E_PFHMC_SDCMD, val3); \
139 wr32((hw), I40E_PFHMC_PDINV, \
Di40e_adminq.c275 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
276 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
279 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
281 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
282 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
304 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
305 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
308 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
310 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
311 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
[all …]
Di40e_ptp.c72 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); in i40e_ptp_write()
73 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); in i40e_ptp_write()
132 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); in i40e_ptp_adjfreq()
133 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); in i40e_ptp_adjfreq()
498 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); in i40e_ptp_set_increment()
499 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); in i40e_ptp_set_increment()
625 wr32(hw, I40E_PRTTSYN_CTL0, regval); in i40e_ptp_set_timestamp_mode()
632 wr32(hw, I40E_PFINT_ICR0_ENA, regval); in i40e_ptp_set_timestamp_mode()
645 wr32(hw, I40E_PRTTSYN_CTL1, regval); in i40e_ptp_set_timestamp_mode()
828 wr32(hw, I40E_PRTTSYN_CTL0, regval); in i40e_ptp_init()
[all …]
Di40e_diag.c25 wr32(hw, reg, (pat & mask)); in i40e_diag_reg_pattern_test()
35 wr32(hw, reg, orig_val); in i40e_diag_reg_pattern_test()
/Linux-v5.10/drivers/net/ethernet/intel/ice/
Dice_controlq.c263 wr32(hw, ring->head, 0); in ice_cfg_cq_regs()
264 wr32(hw, ring->tail, 0); in ice_cfg_cq_regs()
267 wr32(hw, ring->len, (num_entries | ring->len_ena_mask)); in ice_cfg_cq_regs()
268 wr32(hw, ring->bal, lower_32_bits(ring->desc_buf.pa)); in ice_cfg_cq_regs()
269 wr32(hw, ring->bah, upper_32_bits(ring->desc_buf.pa)); in ice_cfg_cq_regs()
308 wr32(hw, cq->rq.tail, (u32)(cq->num_rq_entries - 1)); in ice_cfg_rq_regs()
477 wr32(hw, cq->sq.head, 0); in ice_shutdown_sq()
478 wr32(hw, cq->sq.tail, 0); in ice_shutdown_sq()
479 wr32(hw, cq->sq.len, 0); in ice_shutdown_sq()
480 wr32(hw, cq->sq.bal, 0); in ice_shutdown_sq()
[all …]
Dice_base.c197 wr32(hw, GLINT_CTL, regval); in ice_cfg_itr_gran()
493 wr32(hw, QRX_CTRL(pf_q), rx_reg); in ice_vsi_ctrl_one_rx_ring()
706 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), in ice_cfg_itr()
716 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), in ice_cfg_itr()
743 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val); in ice_cfg_txq_interrupt()
747 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]), in ice_cfg_txq_interrupt()
775 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val); in ice_cfg_rxq_interrupt()
787 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), in ice_trigger_sw_intr()
815 wr32(hw, QINT_TQCTL(ring->reg_idx), val); in ice_vsi_stop_tx_ring()
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/core/
Dgpuobj.c77 .wr32 = nvkm_gpuobj_wr32_fast,
85 .wr32 = nvkm_gpuobj_heap_wr32,
140 .wr32 = nvkm_gpuobj_wr32_fast,
148 .wr32 = nvkm_gpuobj_wr32,
/Linux-v5.10/drivers/net/fjes/
Dfjes_hw.c61 wr32(XSCT_DCTL, dctl.reg); in fjes_hw_reset()
177 wr32(XSCT_REQBL, (__le32)(param->req_len)); in fjes_hw_init_command_registers()
179 wr32(XSCT_RESPBL, (__le32)(param->res_len)); in fjes_hw_init_command_registers()
182 wr32(XSCT_REQBAL, in fjes_hw_init_command_registers()
184 wr32(XSCT_REQBAH, in fjes_hw_init_command_registers()
188 wr32(XSCT_RESPBAL, in fjes_hw_init_command_registers()
190 wr32(XSCT_RESPBAH, in fjes_hw_init_command_registers()
194 wr32(XSCT_SHSTSAL, in fjes_hw_init_command_registers()
196 wr32(XSCT_SHSTSAH, in fjes_hw_init_command_registers()
380 wr32(XSCT_CR, cr.reg); in fjes_hw_issue_request_command()
[all …]

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