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Searched refs:wptr_offs (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c75 unsigned wptr_offs, rptr_offs; in amdgpu_ih_ring_init() local
77 r = amdgpu_device_wb_get(adev, &wptr_offs); in amdgpu_ih_ring_init()
83 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
93 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
98 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; in amdgpu_ih_ring_init()
Damdgpu_ring.c202 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); in amdgpu_ring_init()
294 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); in amdgpu_ring_fini()
Djpeg_v3_0.c424 return adev->wb.wb[ring->wptr_offs]; in jpeg_v3_0_dec_ring_get_wptr()
441 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v3_0_dec_ring_set_wptr()
Djpeg_v2_5.c404 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_5_dec_ring_get_wptr()
421 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_5_dec_ring_set_wptr()
Dsdma_v5_2.c278 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v5_2_ring_get_wptr()
307 ring->wptr_offs, in sdma_v5_2_ring_set_wptr()
311 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
312 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
622 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v5_2_gfx_resume()
Dvcn_v2_0.c1336 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_dec_ring_get_wptr()
1357 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_dec_ring_set_wptr()
1560 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1565 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1584 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
1591 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
Dvcn_v2_5.c1494 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_dec_ring_get_wptr()
1511 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_dec_ring_set_wptr()
1578 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1583 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1602 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
1609 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
Dsdma_v5_0.c325 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v5_0_ring_get_wptr()
354 ring->wptr_offs, in sdma_v5_0_ring_set_wptr()
358 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
359 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
683 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v5_0_gfx_resume()
Dsdma_v4_0.c717 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_ring_get_wptr()
743 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_ring_set_wptr()
749 ring->wptr_offs, in sdma_v4_0_ring_set_wptr()
786 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_page_ring_get_wptr()
808 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_page_ring_set_wptr()
1194 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_gfx_resume()
1285 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_page_resume()
Djpeg_v2_0.c428 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_0_dec_ring_get_wptr()
445 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_0_dec_ring_set_wptr()
Dmes_v10_1.c49 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], in mes_v10_1_ring_set_wptr()
68 &ring->adev->wb.wb[ring->wptr_offs]); in mes_v10_1_ring_get_wptr()
682 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in mes_v10_1_mqd_init()
Dsdma_v3_0.c370 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; in sdma_v3_0_ring_get_wptr()
390 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
395 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
714 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v3_0_gfx_resume()
Dvcn_v3_0.c1634 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_dec_ring_get_wptr()
1651 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_dec_ring_set_wptr()
1718 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_enc_ring_get_wptr()
1723 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_enc_ring_get_wptr()
1742 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_enc_ring_set_wptr()
1749 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_enc_ring_set_wptr()
Dvce_v4_0.c85 return adev->wb.wb[ring->wptr_offs]; in vce_v4_0_ring_get_wptr()
108 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
179 adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0; in vce_v4_0_mmsch_start()
Damdgpu_ring.h230 unsigned wptr_offs; member
Duvd_v7_0.c121 return adev->wb.wb[ring->wptr_offs]; in uvd_v7_0_enc_ring_get_wptr()
156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
738 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; in uvd_v7_0_mmsch_start()
Dgfx_v9_0.c830 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_kiq_map_queues()
3275 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_cp_gfx_resume()
3493 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_mqd_init()
3752 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); in gfx_v9_0_kcq_init_queue()
5165 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_gfx()
5180 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_gfx()
5354 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_compute()
5366 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_compute()
Dgfx_v10_0.c3235 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx10_kiq_map_queues()
5921 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
5958 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
6170 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_gfx_mqd_init()
6279 adev->wb.wb[ring->wptr_offs] = 0; in gfx_v10_0_gfx_init_queue()
6459 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_compute_mqd_init()
6679 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); in gfx_v10_0_kcq_init_queue()
7700 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_gfx()
7715 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v10_0_ring_set_wptr_gfx()
7734 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_compute()
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Dgfx_v8_0.c4304 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_cp_gfx_resume()
4387 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_kiq_kcq_enable()
4517 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_mqd_init()
6048 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_gfx()
6059 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_gfx()
6259 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_compute()
6267 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_compute()
Dgfx_v7_0.c2677 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v7_0_ring_get_wptr_compute()
2685 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v7_0_ring_set_wptr_compute()
2981 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_mqd_init()
/Linux-v5.10/drivers/gpu/drm/radeon/
Dcik.c4174 wptr = rdev->wb.wb[ring->wptr_offs/4]; in cik_compute_get_wptr()
4190 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; in cik_compute_set_wptr()
8428 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET; in cik_startup()
8440 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET; in cik_startup()
Dradeon.h866 unsigned wptr_offs; member