| /Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_vm.c | 130 adev->vm_manager.block_size; in amdgpu_vm_level_shift()
151 adev->vm_manager.root_level); in amdgpu_vm_num_entries()
153 if (level == adev->vm_manager.root_level) in amdgpu_vm_num_entries()
155 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) in amdgpu_vm_num_entries()
177 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_num_ats_entries()
193 if (level <= adev->vm_manager.root_level) in amdgpu_vm_entries_mask()
397 cursor->level = adev->vm_manager.root_level; in amdgpu_vm_pt_start()
744 unsigned level = adev->vm_manager.root_level; in amdgpu_vm_clear_bo()
1033 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
1072 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_flush()
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| D | amdgpu_ids.c | 203 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
226 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
227 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
339 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
412 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab()
474 id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_alloc_reserved()
501 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_free_reserved()
524 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_reset()
551 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_reset_all()
571 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_mgr_init()
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| D | amdgpu_vm.h | 51 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
363 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib…
364 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->wri…
365 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_fu…
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| D | gfxhub_v1_0.c | 102 adev->vm_manager.vram_base_offset; in gfxhub_v1_0_init_system_aperture_regs()
215 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
216 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
257 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
260 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
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| D | gfxhub_v2_0.c | 169 + adev->vm_manager.vram_base_offset; in gfxhub_v2_0_init_system_aperture_regs()
295 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
312 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
325 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
328 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
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| D | gmc_v6_0.c | 445 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()
504 field = adev->vm_manager.fragment_size; in gmc_v6_0_gart_enable()
528 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
549 ((adev->vm_manager.block_size - 9) in gmc_v6_0_gart_enable()
878 adev->vm_manager.first_kfd_vmid = 8; in gmc_v6_0_sw_init()
886 adev->vm_manager.vram_base_offset = tmp; in gmc_v6_0_sw_init()
888 adev->vm_manager.vram_base_offset = 0; in gmc_v6_0_sw_init()
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| D | gfxhub_v2_1.c | 168 + adev->vm_manager.vram_base_offset; in gfxhub_v2_1_init_system_aperture_regs()
301 adev->vm_manager.num_level); in gfxhub_v2_1_setup_vmid_config()
318 adev->vm_manager.block_size - 9); in gfxhub_v2_1_setup_vmid_config()
331 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
334 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
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| D | mmhub_v2_0.c | 213 adev->vm_manager.vram_base_offset; in mmhub_v2_0_init_system_aperture_regs()
350 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
368 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
381 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
384 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
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| D | mmhub_v1_0.c | 118 adev->vm_manager.vram_base_offset; in mmhub_v1_0_init_system_aperture_regs()
238 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
239 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
280 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
283 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
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| D | gmc_v7_0.c | 574 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
646 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
675 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
693 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1053 adev->vm_manager.first_kfd_vmid = 8; in gmc_v7_0_sw_init()
1061 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1063 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
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| D | amdgpu_csa.c | 29 uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; in amdgpu_csa_vaddr()
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| D | gmc_v8_0.c | 800 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
873 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
917 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
942 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
1178 adev->vm_manager.first_kfd_vmid = 8; in gmc_v8_0_sw_init()
1186 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1188 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
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| D | gmc_v10_0.c | 537 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v10_0_get_vm_pde()
703 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v10_0_vram_gtt_location()
706 adev->vm_manager.vram_base_offset += in gmc_v10_0_vram_gtt_location()
884 adev->vm_manager.first_kfd_vmid = 8; in gmc_v10_0_sw_init()
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| D | amdgpu_amdkfd.c | 125 ((1 << adev->vm_manager.first_kfd_vmid) - 1), in amdgpu_amdkfd_device_init()
128 .gpuvm_size = min(adev->vm_manager.max_pfn in amdgpu_amdkfd_device_init()
659 return vmid >= adev->vm_manager.first_kfd_vmid; in amdgpu_amdkfd_is_kfd_vmid()
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| D | gmc_v9_0.c | 1036 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v9_0_get_vm_pde()
1246 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v9_0_vram_gtt_location()
1249 adev->vm_manager.vram_base_offset += in gmc_v9_0_vram_gtt_location()
1393 adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1495 adev->vm_manager.first_kfd_vmid = in gmc_v9_0_sw_init()
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| D | si_dma.c | 841 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; in si_dma_set_vm_pte_funcs()
843 adev->vm_manager.vm_pte_scheds[i] = in si_dma_set_vm_pte_funcs()
846 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()
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| D | amdgpu_vm_sdma.c | 250 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * in amdgpu_vm_sdma_update()
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| D | mmhub_v9_4.c | 140 adev->vm_manager.vram_base_offset; in mmhub_v9_4_init_system_aperture_regs()
311 adev->vm_manager.num_level); in mmhub_v9_4_setup_vmid_config()
329 adev->vm_manager.block_size - 9); in mmhub_v9_4_setup_vmid_config()
349 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v9_4_setup_vmid_config()
354 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v9_4_setup_vmid_config()
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| D | sdma_v2_4.c | 1266 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; in sdma_v2_4_set_vm_pte_funcs()
1268 adev->vm_manager.vm_pte_scheds[i] = in sdma_v2_4_set_vm_pte_funcs()
1271 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v2_4_set_vm_pte_funcs()
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| D | sdma_v5_2.c | 1763 if (adev->vm_manager.vm_pte_funcs == NULL) { in sdma_v5_2_set_vm_pte_funcs()
1764 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; in sdma_v5_2_set_vm_pte_funcs()
1766 adev->vm_manager.vm_pte_scheds[i] = in sdma_v5_2_set_vm_pte_funcs()
1769 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_2_set_vm_pte_funcs()
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| D | cik_sdma.c | 1375 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; in cik_sdma_set_vm_pte_funcs()
1377 adev->vm_manager.vm_pte_scheds[i] = in cik_sdma_set_vm_pte_funcs()
1380 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in cik_sdma_set_vm_pte_funcs()
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| D | sdma_v5_0.c | 1766 if (adev->vm_manager.vm_pte_funcs == NULL) { in sdma_v5_0_set_vm_pte_funcs()
1767 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; in sdma_v5_0_set_vm_pte_funcs()
1769 adev->vm_manager.vm_pte_scheds[i] = in sdma_v5_0_set_vm_pte_funcs()
1772 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_0_set_vm_pte_funcs()
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| D | sdma_v3_0.c | 1704 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; in sdma_v3_0_set_vm_pte_funcs()
1706 adev->vm_manager.vm_pte_scheds[i] = in sdma_v3_0_set_vm_pte_funcs()
1709 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v3_0_set_vm_pte_funcs()
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| /Linux-v5.10/drivers/gpu/drm/radeon/ |
| D | radeon_vm.c | 62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
188 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
195 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
196 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
215 return rdev->vm_manager.active[choices[i]]; in radeon_vm_grab_id()
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| D | ni.c | 1326 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1328 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1363 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
2509 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2514 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2516 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
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