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Searched refs:vclk_div (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/meson/
Dmeson_vclk.c372 unsigned int vclk_div; member
384 .vclk_div = 1,
396 .vclk_div = 1,
408 .vclk_div = 1,
420 .vclk_div = 1,
432 .vclk_div = 1,
444 .vclk_div = 2,
456 .vclk_div = 1,
468 .vclk_div = 1,
810 unsigned int vid_pll_div, unsigned int vclk_div, in meson_vclk_set() argument
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/Linux-v5.10/drivers/gpu/drm/radeon/
Dradeon_uvd.c979 unsigned vclk_div, dclk_div, score; in radeon_uvd_calc_upll_dividers() local
990 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
992 if (vclk_div > pd_max) in radeon_uvd_calc_upll_dividers()
1002 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
1007 *optimal_vclk_div = vclk_div; in radeon_uvd_calc_upll_dividers()
Drv770.c53 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
73 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
78 vclk_div -= 1; in rv770_set_uvd_clocks()
101 UPLL_SW_HILEN(vclk_div >> 1) | in rv770_set_uvd_clocks()
102 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in rv770_set_uvd_clocks()
Dr600.c205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
234 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
261 UPLL_SW_HILEN(vclk_div >> 1) | in r600_set_uvd_clocks()
262 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in r600_set_uvd_clocks()
Devergreen.c1195 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1214 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1253 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in evergreen_set_uvd_clocks()
Dsi.c6999 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
7017 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7058 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dsi.c1616 unsigned vclk_div, dclk_div, score; in si_calc_upll_dividers() local
1627 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk, in si_calc_upll_dividers()
1629 if (vclk_div > pd_max) in si_calc_upll_dividers()
1639 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1644 *optimal_vclk_div = vclk_div; in si_calc_upll_dividers()
1661 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
1679 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
1722 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()