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Searched refs:ufshcd_writel (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.10/drivers/scsi/ufs/
Dufshcd-crypto.c35 ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in ufshcd_program_key()
37 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]), in ufshcd_program_key()
41 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]), in ufshcd_program_key()
44 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]), in ufshcd_program_key()
Dcdns-pltfrm.c133 ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV); in cdns_ufs_set_hclkdiv()
243 ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1); in cdns_ufs_m31_16nm_phy_initialization()
Dufs-mediatek.c228 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk()
230 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk()
286 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); in ufs_mtk_wait_link_state()
874 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); in ufs_mtk_dbg_register_dump()
Dufshcd-dwc.c44 ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV); in ufshcd_dwc_program_clk_div()
Dufs-qcom.c340 ufshcd_writel(hba, in ufs_qcom_enable_hw_clk_gating()
437 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); in ufs_qcom_cfg_timers()
499 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us, in ufs_qcom_cfg_timers()
509 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), in ufs_qcom_cfg_timers()
1258 ufshcd_writel(hba, reg, REG_UFS_CFG1); in ufs_qcom_print_hw_debug_reg_all()
Dufshcd.c686 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR); in ufshcd_utrl_clear()
688 ufshcd_writel(hba, ~(1 << pos), in ufshcd_utrl_clear()
700 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); in ufshcd_utmrl_clear()
702 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); in ufshcd_utmrl_clear()
810 ufshcd_writel(hba, INT_AGGR_ENABLE | in ufshcd_reset_intr_aggr()
824 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | in ufshcd_config_intr_aggr()
836 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); in ufshcd_disable_intr_aggr()
847 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, in ufshcd_enable_run_stop_reg()
849 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, in ufshcd_enable_run_stop_reg()
864 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); in ufshcd_hba_start()
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Dufs-hisi.c230 ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV); in ufs_hisi_link_startup_pre_change()
235 ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); in ufs_hisi_link_startup_pre_change()
Dufshcd.h850 #define ufshcd_writel(hba, val, reg) \ macro
869 ufshcd_writel(hba, tmp, reg); in ufshcd_rmwl()