Searched refs:tier (Results 1 – 11 of 11) sorted by relevance
19 - systemport,num-tier2-arb: number of tier 2 arbiters, an integer20 - systemport,num-tier1-arb: number of tier 1 arbiters, an integer
54 The lower tier consists of a single dm multipath device for each member.61 The upper tier consists of a single dm-switch device. This device uses63 lower tier device to route the I/O. By using a bitmap we are able to
78 u32 tier; member
91 writel_relaxed(timer->context.tier, timer->irq_ena); in omap_timer_restore_context()106 timer->context.tier = readl_relaxed(timer->irq_ena); in omap_timer_save_context()
62 u16 tier; member
107 dst[i++] = FIELD_PREP(GENMASK(31, 16), param->tier) | in allegro_encode_config_blob()
934 param->tier = 0; in fill_create_channel_param()
437 u8 tier; member
1463 p_hevc->tier = 0; in s5p_mfc_set_enc_params_hevc()1475 reg |= (p_hevc->tier << 16); in s5p_mfc_set_enc_params_hevc()
2088 p->codec.hevc.tier = ctrl->val; in s5p_mfc_enc_s_ctrl()
3625 .. _v4l2-hevc-tier:3633 rate. Setting the flag to 0 selects HEVC tier as Main tier and setting3634 this flag to 1 indicates High tier. High tier is for applications requiring3648 - Main tier.3650 - High tier.
