| /Linux-v5.10/drivers/clk/ti/ |
| D | clkt_dflt.c | 68 if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) in _wait_idlest_generic()
103 if (!(ti_clk_ll_ops->clk_readl(&companion_reg) & in _omap2_module_wait_ready()
109 r = ti_clk_ll_ops->cm_split_idlest_reg(&idlest_reg, &prcm_mod, in _omap2_module_wait_ready()
116 ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id, in _omap2_module_wait_ready()
217 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap2_dflt_clk_enable()
228 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_enable()
233 ti_clk_ll_ops->clk_writel(v, &clk->enable_reg); in omap2_dflt_clk_enable()
234 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()
258 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_disable()
263 ti_clk_ll_ops->clk_writel(v, &clk->enable_reg); in omap2_dflt_clk_disable()
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| D | dpll3xxx.c | 54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
73 while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) in _omap3_wait_dpll_status()
151 if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) == in _omap3_noncore_dpll_lock()
317 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()
320 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in omap3_noncore_dpll_program()
324 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap3_noncore_dpll_program()
370 ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg); in omap3_noncore_dpll_program()
374 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()
390 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in omap3_noncore_dpll_program()
[all …]
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| D | apll.c | 58 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable()
63 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_enable()
66 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_enable()
71 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable()
102 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_disable()
105 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_disable()
116 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_is_enabled()
247 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_is_enabled()
273 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_enable()
276 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in omap2_apll_enable()
[all …]
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| D | clkt_iclk.c | 36 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_allow_idle()
38 ti_clk_ll_ops->clk_writel(v, &r); in omap2_clkt_iclk_allow_idle()
51 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_deny_idle()
53 ti_clk_ll_ops->clk_writel(v, &r); in omap2_clkt_iclk_deny_idle()
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| D | dpll44xx.c | 49 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
52 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
67 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
70 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
128 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap4_dpll_regm4xen_recalc()
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| D | clk.c | 36 struct ti_clk_ll_ops *ti_clk_ll_ops; variable
107 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops) in ti_clk_setup_ll_ops()
109 if (ti_clk_ll_ops) { in ti_clk_setup_ll_ops()
114 ti_clk_ll_ops = ops; in ti_clk_setup_ll_ops()
303 ti_clk_ll_ops->clk_rmw(latch, latch, reg); in ti_clk_latch()
304 ti_clk_ll_ops->clk_rmw(0, latch, reg); in ti_clk_latch()
305 ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */ in ti_clk_latch()
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| D | autoidle.c | 129 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _allow_autoidle()
136 ti_clk_ll_ops->clk_writel(val, &clk->reg); in _allow_autoidle()
143 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _deny_autoidle()
150 ti_clk_ll_ops->clk_writel(val, &clk->reg); in _deny_autoidle()
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| D | clkctrl.c | 145 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in _omap4_clkctrl_clk_enable()
158 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_enable()
163 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); in _omap4_clkctrl_clk_enable()
169 while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_enable()
188 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_disable()
192 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); in _omap4_clkctrl_clk_disable()
198 while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_disable()
208 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in _omap4_clkctrl_clk_disable()
216 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_is_enabled()
747 val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg); in ti_clk_is_in_standby()
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| D | clockdomain.c | 61 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap2_clkops_enable_clkdm()
95 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in omap2_clkops_disable_clkdm()
117 clkdm = ti_clk_ll_ops->clkdm_lookup(clk->clkdm_name); in omap2_init_clk_clkdm()
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| D | divider.c | 107 val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; in ti_clk_divider_recalc_rate()
264 val = ti_clk_ll_ops->clk_readl(÷r->reg); in ti_clk_divider_set_rate()
267 ti_clk_ll_ops->clk_writel(val, ÷r->reg); in ti_clk_divider_set_rate()
285 val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; in clk_divider_save_context()
302 val = ti_clk_ll_ops->clk_readl(÷r->reg); in clk_divider_restore_context()
305 ti_clk_ll_ops->clk_writel(val, ÷r->reg); in clk_divider_restore_context()
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| D | clkt_dpll.c | 213 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_init_dpll_parent()
249 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_get_dpll_rate()
256 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap2_get_dpll_rate()
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| D | gate.c | 82 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
87 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
90 ti_clk_ll_ops->clk_writel(orig_v, &parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
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| D | mux.c | 42 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
84 val = ti_clk_ll_ops->clk_readl(&mux->reg); in ti_clk_mux_set_parent()
88 ti_clk_ll_ops->clk_writel(val, &mux->reg); in ti_clk_mux_set_parent()
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| D | clock.h | 315 extern struct ti_clk_ll_ops *ti_clk_ll_ops;
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| /Linux-v5.10/include/linux/clk/ |
| D | ti.h | 230 struct ti_clk_ll_ops { struct
261 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops); argument
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| /Linux-v5.10/arch/arm/mach-omap2/ |
| D | clock.h | 64 extern struct ti_clk_ll_ops omap_clk_ll_ops;
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| D | clock.c | 54 struct ti_clk_ll_ops omap_clk_ll_ops = {
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