Searched refs:tg_inst (Results 1 – 9 of 9) sorted by relevance
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_hwseq.c | 177 unsigned int tg_inst) in dce_crtc_switch_to_clk_src() argument 180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src() 186 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src() 190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src() 196 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src() 200 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src() 201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src() 205 clk_src->id, tg_inst); in dce_crtc_switch_to_clk_src()
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| D | dce_stream_encoder.c | 1588 int tg_inst, bool enable) in setup_stereo_sync() argument 1591 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync() 1597 int tg_inst) in dig_connect_to_otg() argument 1601 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in dig_connect_to_otg() 1607 uint32_t tg_inst = 0; in dig_source_otg() local 1610 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg() 1612 return tg_inst; in dig_source_otg()
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| D | dce_hwseq.h | 862 unsigned int tg_inst);
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/virtual/ |
| D | virtual_stream_encoder.c | 93 int tg_inst) in virtual_dig_connect_to_otg() argument 98 int tg_inst, in virtual_setup_stereo_sync() argument
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | stream_encoder.h | 201 int tg_inst, 209 int tg_inst);
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_stream_encoder.c | 1525 int tg_inst, bool enable) in enc1_setup_stereo_sync() argument 1528 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in enc1_setup_stereo_sync() 1534 int tg_inst) in enc1_dig_connect_to_otg() argument 1538 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in enc1_dig_connect_to_otg() 1544 uint32_t tg_inst = 0; in enc1_dig_source_otg() local 1547 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in enc1_dig_source_otg() 1549 return tg_inst; in enc1_dig_source_otg()
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| D | dcn10_stream_encoder.h | 616 int tg_inst, bool enable); 648 int tg_inst);
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_resource.c | 1995 unsigned int i, inst, tg_inst = 0; in acquire_resource_from_hw_enabled_state() local 2008 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( in acquire_resource_from_hw_enabled_state() 2018 if (tg_inst >= pool->timing_generator_count) in acquire_resource_from_hw_enabled_state() 2021 if (!res_ctx->pipe_ctx[tg_inst].stream) { in acquire_resource_from_hw_enabled_state() 2022 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; in acquire_resource_from_hw_enabled_state() 2024 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; in acquire_resource_from_hw_enabled_state() 2025 pipe_ctx->plane_res.mi = pool->mis[tg_inst]; in acquire_resource_from_hw_enabled_state() 2026 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; in acquire_resource_from_hw_enabled_state() 2027 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; in acquire_resource_from_hw_enabled_state() 2028 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; in acquire_resource_from_hw_enabled_state() [all …]
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| D | dc.c | 870 unsigned int enc_inst, tg_inst = 0; in disable_vbios_mode_if_required() local 877 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg( in disable_vbios_mode_if_required() 885 tg_inst, &pix_clk_100hz); in disable_vbios_mode_if_required() 1165 unsigned int i, enc_inst, tg_inst = 0; in dc_validate_seamless_boot_timing() local 1186 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg( in dc_validate_seamless_boot_timing() 1196 if (tg_inst >= dc->res_pool->timing_generator_count) in dc_validate_seamless_boot_timing() 1199 tg = dc->res_pool->timing_generators[tg_inst]; in dc_validate_seamless_boot_timing() 1248 tg_inst, &pix_clk_100hz); in dc_validate_seamless_boot_timing()
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