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Searched refs:tCCS_min (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.10/drivers/mtd/nand/raw/
Dnand_timings.c28 .tCCS_min = 500000,
73 .tCCS_min = 500000,
118 .tCCS_min = 500000,
163 .tCCS_min = 500000,
208 .tCCS_min = 500000,
253 .tCCS_min = 500000,
315 if (spec_timings->tCCS_min <= onfi_timings->tCCS_min && in onfi_find_closest_sdr_mode()
385 timings->tCCS_min = 1000UL * onfi->tCCS; in onfi_fill_interface_config()
Dnand_legacy.c372 ndelay(sdr->tCCS_min / 1000); in nand_ccs_delay()
Dmarvell_nand.c2398 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2400 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
Ddenali.c824 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); in denali_setup_interface()
Dnand_base.c1210 PSEC_TO_NSEC(sdr->tCCS_min)), in nand_change_read_column_op()
1514 NAND_OP_ADDR(2, addrs, PSEC_TO_NSEC(sdr->tCCS_min)), in nand_change_write_column_op()
Dcadence-nand-controller.c2472 tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period); in cadence_nand_setup_interface()
/Linux-v5.10/include/linux/mtd/
Drawnand.h438 u32 tCCS_min; member