| /Linux-v5.10/arch/mips/kernel/ |
| D | cps-vec.S | 174 move a1, t9
318 li t9, 0
327 mfc0 t9, CP0_GLOBALNUMBER
328 andi t9, t9, MIPS_GLOBALNUMBER_VP
347 mfc0 t9, $15, 1
348 and t9, t9, t1
353 mul v1, t9, t1
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| D | octeon_switch.S | 49 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
54 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
66 LONG_L t9, TASK_STACK_CANARY(a1)
67 LONG_S t9, 0(t8)
100 dmfc0 t9, $9,7 /* CvmCtl register. */
109 bbit1 t9, 28, 1f
117 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
263 dmfc0 t9, $9,7 /* CvmCtl register. */
274 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
284 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
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| D | r2300_switch.S | 41 LONG_L t9, TASK_STACK_CANARY(a1)
42 LONG_S t9, 0(t8)
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| D | r4k_switch.S | 36 LONG_L t9, TASK_STACK_CANARY(a1)
37 LONG_S t9, 0(t8)
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| D | cps-vec-ns16550.S | 37 1: UART_L t0, UART_LSR_OFS(t9)
40 UART_S a0, UART_TX_OFS(t9)
176 li t9, CKSEG1ADDR(CONFIG_MIPS_CPS_NS16550_BASE)
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| D | pm-cps.c | 76 t8, t9, k0, k1, gp, sp, fp, ra, enumerator
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| /Linux-v5.10/arch/mips/include/asm/ |
| D | regdef.h | 51 #define t9 $25 macro
94 #define t9 $25 /* callee address for PIC/temp */ macro
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| /Linux-v5.10/arch/ia64/lib/ |
| D | copy_page_mck.S | 84 #define t9 t5 // alias! macro
163 (p[D]) ld8 t9 = [src0], 3*8
170 (p[D]) st8 [dst0] = t9, 3*8
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| D | memcpy_mck.S | 53 #define t9 t5 // alias! macro
243 EX(.ex_handler, (p[D]) ld8 t9 = [src0], 3*8)
250 EX(.ex_handler, (p[D]) st8 [dst0] = t9, 3*8)
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| /Linux-v5.10/arch/alpha/lib/ |
| D | stxcpy.S | 39 .frame sp, 0, t9
91 ret (t9) # .. e1 :
99 .frame sp, 0, t9
230 ret (t9) # .. e1 :
288 ret (t9) # e1 :
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| D | ev6-stxcpy.S | 50 .frame sp, 0, t9
109 ret (t9) # L0 : Latency=3
119 .frame sp, 0, t9
259 ret (t9) # L0 : Latency=3
318 ret (t9) # e1 :
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| D | stxncpy.S | 47 .frame sp, 0, t9, 0
105 ret (t9) # e1 :
118 .frame sp, 0, t9, 0
266 ret (t9) # .. e1 :
344 ret (t9) # .. e1 :
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| D | ev6-stxncpy.S | 58 .frame sp, 0, t9, 0
133 ret (t9) # L0 : Latency=3
150 .frame sp, 0, t9, 0
312 ret (t9) # L0 : Latency=3
393 ret (t9) # L0 : Latency=3
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| /Linux-v5.10/arch/alpha/include/uapi/asm/ |
| D | regdef.h | 33 #define t9 $23 macro
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| /Linux-v5.10/arch/arm64/crypto/ |
| D | ghash-ce-core.S | 30 t9 .req v16
105 pmull\t t9.8h, \ad, \b4\().\nb // K = A*B4
114 uzp1 t6.2d, t7.2d, t9.2d
115 uzp2 t7.2d, t7.2d, t9.2d
132 zip2 t9.2d, t6.2d, t7.2d
138 ext t9.16b, t9.16b, t9.16b, #12
141 eor t7.16b, t7.16b, t9.16b
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| D | crct10dif-ce-core.S | 89 t9 .req v23
145 pmull t9.8h, ad.8b, bd3.8b // I = A*B3
159 pmull2 t9.8h, ad.16b, bd3.16b // I = A*B3
164 eor t6.16b, t6.16b, t9.16b // N = I + J
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| /Linux-v5.10/drivers/gpu/drm/i915/display/ |
| D | intel_bios.h | 52 u16 t9; member
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| D | intel_dp.c | 6931 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
6950 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
6961 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || in intel_pps_verify_state()
7008 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ in intel_dp_init_panel_power_sequencer()
7025 assign_final(t9); in intel_dp_init_panel_power_sequencer()
7033 intel_dp->backlight_off_delay = get_delay(t9); in intel_dp_init_panel_power_sequencer()
7056 final->t9 = 1; in intel_dp_init_panel_power_sequencer()
7109 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in intel_dp_init_panel_power_sequencer_registers()
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| /Linux-v5.10/arch/mips/lib/ |
| D | memset.S | 103 move t9, a1
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| /Linux-v5.10/drivers/gpu/drm/gma500/ |
| D | intel_bios.h | 447 u16 t9; member
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| D | intel_bios.c | 84 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
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| D | cdv_intel_dp.c | 2049 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> in cdv_intel_dp_init()
2059 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); in cdv_intel_dp_init()
2064 intel_dp->backlight_off_delay = cur.t9 / 10; in cdv_intel_dp_init()
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| /Linux-v5.10/arch/mips/crypto/ |
| D | chacha-core.S | 20 #define X9 $t9
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