Searched refs:sys_clock_freq (Results 1 – 3 of 3) sorted by relevance
128 u16 sys_clock_freq; member1648 state->sys_clock_freq = (u16) sysClockFreq; in CorrectSysClockDeviation()1842 1 << 28, state->sys_clock_freq); in SetFrequencyShift()1851 1 << 28, state->sys_clock_freq); in SetFrequencyShift()2374 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, in DRX_Start()2553 state->sys_clock_freq = 48000; in CDRXD()2570 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * in CDRXD()2648 state->sys_clock_freq = in DRXD_init()
1828 s32 sys_clock_freq; member2223 #define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq)
2410 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000; in init_hi()2938 (u32) (common_attr->sys_clock_freq / 8))) / in ctrl_set_cfg_mpeg_output()2973 (u32) (common_attr->sys_clock_freq / 8))) / in ctrl_set_cfg_mpeg_output()3057 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + in ctrl_set_cfg_mpeg_output()3060 frac28(bit_rate, common_attr->sys_clock_freq * 1000); in ctrl_set_cfg_mpeg_output()4816 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; in set_frequency()8023 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; in set_qam()
