Searched refs:src_shift (Results 1 – 7 of 7) sorted by relevance
40 u32 src_shift; member139 hw_index = (readl(clock->reg) >> clock->src_shift) & in cpg_div6_clock_get_parent()160 mask = ~((BIT(clock->src_width) - 1) << clock->src_shift); in cpg_div6_clock_set_parent()163 writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift), in cpg_div6_clock_set_parent()239 clock->src_shift = clock->src_width = 0; in cpg_div6_register()243 clock->src_shift = 6; in cpg_div6_register()248 clock->src_shift = 12; in cpg_div6_register()
29 val = (div << md->hid_shift) | (src << md->src_shift); in mux_div_set_src_div()31 ((BIT(md->src_width) - 1) << md->src_shift); in mux_div_set_src_div()73 s = (val >> md->src_shift); in mux_div_get_src_div()
32 u32 src_shift; member
76 a53cc->src_shift = 8; in qcom_apcs_msm8916_clk_probe()
43 unsigned char src_shift; /* source clock field in the */ member184 .src_shift = _src_shift, \
209 val = (sh_clk_read(clk) >> clk->src_shift); in sh_clk_init_parent()301 ~(((1 << clk->src_width) - 1) << clk->src_shift); in sh_clk_div6_set_parent()303 sh_clk_write(value | (i << clk->src_shift), clk); in sh_clk_div6_set_parent()
151 unsigned int src_shift; member177 .src_shift = s, \717 val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift); in ns2_pin_set_slew()720 val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift; in ns2_pin_set_slew()739 *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK; in ns2_pin_get_slew()
