| /Linux-v5.10/arch/powerpc/mm/ |
| D | slice.c | 34 static void slice_print_mask(const char *label, const struct slice_mask *mask) in slice_print_mask()
48 static void slice_print_mask(const char *label, const struct slice_mask *mask) {} in slice_print_mask()
61 struct slice_mask *ret) in slice_range_to_mask()
117 static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret, in slice_mask_for_free()
139 const struct slice_mask *available, in slice_check_range_fits()
188 const struct slice_mask *mask, int psize) in slice_convert()
193 struct slice_mask *psize_mask, *old_mask; in slice_convert()
262 const struct slice_mask *available, in slice_scan_available()
280 const struct slice_mask *available, in slice_find_area_bottomup()
326 const struct slice_mask *available, in slice_find_area_topdown()
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| /Linux-v5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_sseu_debugfs.c | 40 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
91 sseu->slice_mask |= BIT(s); in gen10_sseu_device_status()
144 sseu->slice_mask |= BIT(s); in gen9_sseu_device_status()
183 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; in bdw_sseu_device_status()
185 if (sseu->slice_mask) { in bdw_sseu_device_status()
187 for (s = 0; s < fls(sseu->slice_mask); s++) in bdw_sseu_device_status()
194 for (s = 0; s < fls(sseu->slice_mask); s++) { in bdw_sseu_device_status()
211 sseu->slice_mask); in i915_print_sseu_info()
213 hweight8(sseu->slice_mask)); in i915_print_sseu_info()
216 for (s = 0; s < fls(sseu->slice_mask); s++) { in i915_print_sseu_info()
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| D | intel_sseu.c | 117 sseu->slice_mask |= BIT(s); in gen11_compute_sseu_info()
203 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> in gen10_sseu_info_init()
277 sseu->slice_mask = BIT(0); in cherryview_sseu_info_init()
335 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; in gen9_sseu_info_init()
354 if (!(sseu->slice_mask & BIT(s))) in gen9_sseu_info_init()
409 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; in gen9_sseu_info_init()
440 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; in bdw_sseu_info_init()
466 if (!(sseu->slice_mask & BIT(s))) in bdw_sseu_info_init()
511 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; in bdw_sseu_info_init()
533 sseu->slice_mask = BIT(0); in hsw_sseu_info_init()
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| D | intel_sseu.h | 27 u8 slice_mask; member
52 u8 slice_mask; member
62 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
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| D | intel_engine_types.h | 622 ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
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| D | intel_workarounds.c | 1119 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { in wa_init_mcr()
1130 slice = fls(sseu->slice_mask) - 1; in wa_init_mcr()
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| /Linux-v5.10/arch/powerpc/include/asm/book3s/64/ |
| D | mmu-hash.h | 696 struct slice_mask { struct
709 struct slice_mask mask_64k; argument
711 struct slice_mask mask_4k;
713 struct slice_mask mask_16m;
714 struct slice_mask mask_16g;
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| D | mmu.h | 165 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize) in slice_mask_for_size()
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| /Linux-v5.10/drivers/crypto/qat/qat_common/ |
| D | icp_qat_fw_loader_handle.h | 18 unsigned int slice_mask; member
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| D | qat_hal.c | 278 ae_reset_csr |= handle->hal_handle->slice_mask << RST_CSR_QAT_LSB; in qat_hal_reset()
450 ae_reset_csr &= ~(handle->hal_handle->slice_mask << RST_CSR_QAT_LSB); in qat_hal_clr_reset()
457 (handle->hal_handle->slice_mask << RST_CSR_QAT_LSB)) & csr); in qat_hal_clr_reset()
461 clk_csr |= handle->hal_handle->slice_mask << 20; in qat_hal_clr_reset()
688 handle->hal_handle->slice_mask = hw_data->accel_mask; in qat_hal_init()
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| /Linux-v5.10/drivers/gpu/drm/i915/ |
| D | i915_query.c | 45 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in query_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in query_topology_info()
76 &sseu->slice_mask, slice_length)) in query_topology_info()
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| D | i915_getparam.c | 147 value = sseu->slice_mask; in i915_getparam_ioctl()
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| D | intel_pm.c | 4062 u32 slice_mask = 0; in skl_ddb_dbuf_slice_mask() local
4080 slice_mask |= BIT(start_slice); in skl_ddb_dbuf_slice_mask()
4084 return slice_mask; in skl_ddb_dbuf_slice_mask()
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| D | i915_perf.c | 2788 out_sseu->slice_mask = 0x1; in get_default_sseu_config()
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| /Linux-v5.10/drivers/gpu/drm/i915/gem/ |
| D | i915_gem_context.c | 1433 if (!user->slice_mask || !user->subslice_mask || in i915_gem_user_to_context_sseu()
1445 if (overflows_type(user->slice_mask, context->slice_mask) || in i915_gem_user_to_context_sseu()
1454 if (user->slice_mask & ~device->slice_mask) in i915_gem_user_to_context_sseu()
1463 context->slice_mask = user->slice_mask; in i915_gem_user_to_context_sseu()
1470 unsigned int hw_s = hweight8(device->slice_mask); in i915_gem_user_to_context_sseu()
1472 unsigned int req_s = hweight8(context->slice_mask); in i915_gem_user_to_context_sseu()
2461 user_sseu.slice_mask = ce->sseu.slice_mask; in get_sseu()
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| /Linux-v5.10/drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_ads.c | 102 blob->system_info.slice_enabled = hweight8(gt->info.sseu.slice_mask); in __guc_ads_init()
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| /Linux-v5.10/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_context.c | 1153 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1210 hweight32(sseu.slice_mask), spin); in __sseu_test()
1255 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1266 pg_sseu.slice_mask = 1; in __igt_ctx_sseu()
1272 hweight32(engine->sseu.slice_mask), in __igt_ctx_sseu()
1273 hweight32(pg_sseu.slice_mask)); in __igt_ctx_sseu()
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| /Linux-v5.10/tools/include/uapi/drm/ |
| D | i915_drm.h | 1738 __u64 slice_mask; member
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| /Linux-v5.10/include/uapi/drm/ |
| D | i915_drm.h | 1738 __u64 slice_mask; member
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