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Searched refs:sclk_mask (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c215 uint32_t *sclk_mask, in renoir_get_profiling_clk_mask() argument
221 if (sclk_mask) in renoir_get_profiling_clk_mask()
222 *sclk_mask = 0; in renoir_get_profiling_clk_mask()
228 if(sclk_mask) in renoir_get_profiling_clk_mask()
230 *sclk_mask = 3 - 1; in renoir_get_profiling_clk_mask()
827 uint32_t sclk_mask, mclk_mask, soc_mask; in renoir_set_performance_level() local
893 &sclk_mask, in renoir_set_performance_level()
898 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); in renoir_set_performance_level()
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_hwmgr.c1608 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1615 *sclk_mask = 0; in vega12_get_profiling_clk_mask()
1622 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; in vega12_get_profiling_clk_mask()
1628 *sclk_mask = 0; in vega12_get_profiling_clk_mask()
1632 *sclk_mask = gfx_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1662 uint32_t sclk_mask = 0; in vega12_dpm_force_dpm_level() local
1680 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1683 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); in vega12_dpm_force_dpm_level()
Dsmu7_hwmgr.c2757 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
2788 *sclk_mask = count; in smu7_get_profiling_clk()
2793 *sclk_mask = 0; in smu7_get_profiling_clk()
2798 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
2806 *sclk_mask = count; in smu7_get_profiling_clk()
2811 *sclk_mask = 0; in smu7_get_profiling_clk()
2816 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; in smu7_get_profiling_clk()
2835 uint32_t sclk_mask = 0; in smu7_force_dpm_level() local
2840 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
2856 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
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Dvega20_hwmgr.c2486 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2493 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2500 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL; in vega20_get_profiling_clk_mask()
2506 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2510 *sclk_mask = gfx_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2686 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2705 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2708 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); in vega20_dpm_force_dpm_level()
Dvega10_hwmgr.c4091 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4099 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; in vega10_get_profiling_clk_mask()
4107 *sclk_mask = 0; in vega10_get_profiling_clk_mask()
4115 *sclk_mask = 4; in vega10_get_profiling_clk_mask()
4117 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; in vega10_get_profiling_clk_mask()
4210 uint32_t sclk_mask = 0; in vega10_dpm_force_dpm_level() local
4215 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4231 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4234 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); in vega10_dpm_force_dpm_level()